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Commit e9d03335 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/gr/gp100-: use correct registers for zbc colour/depth setup 



These were missed the first time around due to the driver version I traced
using the older registers still.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 7a058a90

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

+22 −15
Original line number Diff line number Diff line
@@ -92,7 +92,7 @@ gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, 
	memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2));

	gr->zbc_color[zbc].format = format;

	nvkm_ltc_zbc_color_get(ltc, zbc, l2);

	gf100_gr_zbc_clear_color(gr, zbc);

	gr->func->zbc->clear_color(gr, zbc);

	return zbc;

}
@@ -137,10 +137,16 @@ gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, 
	gr->zbc_depth[zbc].ds = ds;

	gr->zbc_depth[zbc].l2 = l2;

	nvkm_ltc_zbc_depth_get(ltc, zbc, l2);

	gf100_gr_zbc_clear_depth(gr, zbc);

	gr->func->zbc->clear_depth(gr, zbc);

	return zbc;

}



const struct gf100_gr_func_zbc

gf100_gr_zbc = {

	.clear_color = gf100_gr_zbc_clear_color,

	.clear_depth = gf100_gr_zbc_clear_depth,

};



/*******************************************************************************

 * Graphics object classes

 ******************************************************************************/
@@ -744,21 +750,21 @@ gf100_gr_zbc_init(struct gf100_gr *gr) 
	const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,

			      0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };

	struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;

	int index;

	int index, c = ltc->zbc_min, d = ltc->zbc_min;



	if (!gr->zbc_color[0].format) {

		gf100_gr_zbc_color_get(gr, 1,  & zero[0],   &zero[4]);

		gf100_gr_zbc_color_get(gr, 2,  &  one[0],    &one[4]);

		gf100_gr_zbc_color_get(gr, 4,  &f32_0[0],  &f32_0[4]);

		gf100_gr_zbc_color_get(gr, 4,  &f32_1[0],  &f32_1[4]);

		gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000);

		gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000);

		gf100_gr_zbc_color_get(gr, 1,  & zero[0],   &zero[4]); c++;

		gf100_gr_zbc_color_get(gr, 2,  &  one[0],    &one[4]); c++;

		gf100_gr_zbc_color_get(gr, 4,  &f32_0[0],  &f32_0[4]); c++;

		gf100_gr_zbc_color_get(gr, 4,  &f32_1[0],  &f32_1[4]); c++;

		gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); d++;

		gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); d++;

	}



	for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)

		gf100_gr_zbc_clear_color(gr, index);

	for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)

		gf100_gr_zbc_clear_depth(gr, index);

	for (index = c; index <= ltc->zbc_max; index++)

		gr->func->zbc->clear_color(gr, index);

	for (index = d; index <= ltc->zbc_max; index++)

		gr->func->zbc->clear_depth(gr, index);

}



/**
@@ -2242,6 +2248,7 @@ gf100_gr = { 
	.gpccs.ucode = &gf100_gr_gpccs_ucode,

	.rops = gf100_gr_rops,

	.grctx = &gf100_grctx,

	.zbc = &gf100_gr_zbc,

	.sclass = {

		{ -1, -1, FERMI_TWOD_A },

		{ -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h

+10 −0
Original line number Diff line number Diff line
@@ -129,6 +129,11 @@ int gf100_gr_new_(const struct gf100_gr_func *, struct nvkm_device *, 
		  int, struct nvkm_gr **);

void *gf100_gr_dtor(struct nvkm_gr *);



struct gf100_gr_func_zbc {

	void (*clear_color)(struct gf100_gr *, int zbc);

	void (*clear_depth)(struct gf100_gr *, int zbc);

};



struct gf100_gr_func {

	void (*dtor)(struct gf100_gr *);

	void (*oneinit_tiles)(struct gf100_gr *);
@@ -170,6 +175,7 @@ struct gf100_gr_func { 
	int ppc_nr;

	const struct gf100_grctx_func *grctx;

	const struct nvkm_therm_clkgate_pack *clkgate_pack;

	const struct gf100_gr_func_zbc *zbc;

	struct nvkm_sclass sclass[];

};
@@ -187,6 +193,7 @@ void gf100_gr_init_419eb4(struct gf100_gr *); 
void gf100_gr_init_tex_hww_esr(struct gf100_gr *, int, int);

void gf100_gr_init_shader_exceptions(struct gf100_gr *, int, int);

void gf100_gr_init_400054(struct gf100_gr *);

extern const struct gf100_gr_func_zbc gf100_gr_zbc;



void gf117_gr_init_zcull(struct gf100_gr *);
@@ -212,6 +219,9 @@ void gm200_gr_init_ds_hww_esr_2(struct gf100_gr *); 
void gp100_gr_init_rop_active_fbps(struct gf100_gr *);

void gp100_gr_init_fecs_exceptions(struct gf100_gr *);

void gp100_gr_init_shader_exceptions(struct gf100_gr *, int, int);

extern const struct gf100_gr_func_zbc gp100_gr_zbc;

void gp100_gr_zbc_clear_color(struct gf100_gr *, int);

void gp100_gr_zbc_clear_depth(struct gf100_gr *, int);



void gp102_gr_init_swdx_pes_mask(struct gf100_gr *);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c

+1 −0
Original line number Diff line number Diff line
@@ -134,6 +134,7 @@ gf104_gr = { 
	.gpccs.ucode = &gf100_gr_gpccs_ucode,

	.rops = gf100_gr_rops,

	.grctx = &gf104_grctx,

	.zbc = &gf100_gr_zbc,

	.sclass = {

		{ -1, -1, FERMI_TWOD_A },

		{ -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c

+1 −0
Original line number Diff line number Diff line
@@ -132,6 +132,7 @@ gf108_gr = { 
	.gpccs.ucode = &gf100_gr_gpccs_ucode,

	.rops = gf100_gr_rops,

	.grctx = &gf108_grctx,

	.zbc = &gf100_gr_zbc,

	.sclass = {

		{ -1, -1, FERMI_TWOD_A },

		{ -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c

+1 −0
Original line number Diff line number Diff line
@@ -106,6 +106,7 @@ gf110_gr = { 
	.gpccs.ucode = &gf100_gr_gpccs_ucode,

	.rops = gf100_gr_rops,

	.grctx = &gf110_grctx,

	.zbc = &gf100_gr_zbc,

	.sclass = {

		{ -1, -1, FERMI_TWOD_A },

		{ -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },