Commit 44fefab4 authored Aug 09, 2013 by Stephen Warren

ARM: tegra: Fix Beaver's PCIe lane configuration

Beaver's PCIe lane configuration most closely matches x2 x2 x2 rather
than x4 x1 x1, since clocks 0 and 2 are used, and lanes 0 and 5 are used,
and the only way those align is with a x2 x2 x2 configuration.

Also, disable root port 1; there's nothing connected to it. Root port 0
is the on-board PCIe Ethernet, and port 2 is the mini-PCIe slot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

parent bb034cb5

arch/arm/boot/dts/tegra30-beaver.dts

+4 −4

Original line number	Original line	Diff line number	Diff line
	@@ -18,16 +18,16 @@

	pci@1,0 {		pci@1,0 {
	status = "okay";		status = "okay";
	nvidia,num-lanes = <4>;		nvidia,num-lanes = <2>;
	};		};

	pci@2,0 {		pci@2,0 {
	status = "okay";		nvidia,num-lanes = <2>;
	nvidia,num-lanes = <1>;
	};		};

	pci@3,0 {		pci@3,0 {
	nvidia,num-lanes = <1>;		status = "okay";
			nvidia,num-lanes = <2>;
	};		};
	};		};