Commit bb034cb5 authored Aug 09, 2013 by Thierry Reding Committed by Stephen Warren Aug 12, 2013

ARM: tegra: Enable PCIe controller on Beaver



PCIe lane 0 is connected to an onboard Gigabit Ethernet (RTL8168evl) and
lane 4 is routed to the board's miniPCIe slot.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

parent 89e7ada4

arch/arm/boot/dts/tegra30-beaver.dts

+21 −0

Original line number	Diff line number	Diff line
		@@ -10,6 +10,27 @@
		reg = <0x80000000 0x7ff00000>;
		};

		pcie-controller {
		status = "okay";
		pex-clk-supply = <&sys_3v3_pexs_reg>;
		vdd-supply = <&ldo1_reg>;
		avdd-supply = <&ldo2_reg>;

		pci@1,0 {
		status = "okay";
		nvidia,num-lanes = <4>;
		};

		pci@2,0 {
		status = "okay";
		nvidia,num-lanes = <1>;
		};

		pci@3,0 {
		nvidia,num-lanes = <1>;
		};
		};

		host1x {
		hdmi {
		status = "okay";