ASoC: tlv320aic32x4: Use correct shift definition for DATATYPE bits

Setting the DATATYPE bit field requires shifting our value by 6. Setting
the J value of the PLL also requires a shift by 6. Currently the code
abuses this fact and uses the shift for the PLL register to set the
data-type register. Fix this here by using the definition meant for
this register.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>