Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 38a39a7b authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915/bxt: add WaDisableMaskBasedCammingInRCC workaround 



Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarNick Hoath <nicholas.hoath@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 868434c5

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -5346,6 +5346,10 @@ enum skl_disp_power_wells { 
#define  HDC_FORCE_NON_COHERENT			(1<<4)

#define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)



/* GEN9 chicken */

#define SLICE_ECO_CHICKEN0			0x7308

#define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)



/* WaCatErrorRejectionIssue */

#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030

#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)

drivers/gpu/drm/i915/intel_ringbuffer.c

+9 −0
Original line number Diff line number Diff line
@@ -966,6 +966,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) 
	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,

			  GEN9_CCS_TLB_PREFETCH_ENABLE);



	/*

	 * FIXME: don't apply the following on BXT for stepping C. On BXT A0

	 * the flag reads back as 0.

	 */

	/* WaDisableMaskBasedCammingInRCC:bxtA */

	if (IS_BROXTON(dev))

		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,

				  PIXEL_MASK_CAMMING_DISABLE);



	return 0;

}