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Commit 868434c5 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaround 



Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarNick Hoath <nicholas.hoath@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 32608ca2

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -6104,6 +6104,7 @@ enum skl_disp_power_wells { 
#define GEN8_UCGCTL6				0x9430

#define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)

#define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)

#define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)



#define GEN6_GFXPAUSE				0xA000

#define GEN6_RPNSWREQ				0xA008

drivers/gpu/drm/i915/intel_pm.c

+3 −1
Original line number Diff line number Diff line
@@ -103,10 +103,12 @@ static void bxt_init_clock_gating(struct drm_device *dev) 
	/*

	 * FIXME:

	 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.

	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.

	 */

	 /* WaDisableSDEUnitClockGating:bxt */

	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |

		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);



}