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Commit 30aa7b18 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'thunderx-fixes' 



David Daney says:

====================
net: thunderx: Support pass-2 revision hardware.

With the availability of a new revision of the ThunderX NIC hardware a
few changes to the driver are required.  With these, the driver works
on all currently available hardware revisions.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents ce9d9b8e 34411b68

drivers/net/ethernet/cavium/thunder/nic_main.c

+29 −13
Original line number Diff line number Diff line
@@ -22,7 +22,6 @@ 


struct nicpf {

	struct pci_dev		*pdev;

	u8			rev_id;

	u8			node;

	unsigned int		flags;

	u8			num_vf_en;      /* No of VF enabled */
@@ -44,6 +43,7 @@ struct nicpf { 
	u8			duplex[MAX_LMAC];

	u32			speed[MAX_LMAC];

	u16			cpi_base[MAX_NUM_VFS_SUPPORTED];

	u16			rssi_base[MAX_NUM_VFS_SUPPORTED];

	u16			rss_ind_tbl_size;

	bool			mbx_lock[MAX_NUM_VFS_SUPPORTED];
@@ -54,6 +54,11 @@ struct nicpf { 
	bool			irq_allocated[NIC_PF_MSIX_VECTORS];

};



static inline bool pass1_silicon(struct nicpf *nic)

{

	return nic->pdev->revision < 8;

}



/* Supported devices */

static const struct pci_device_id nic_id_table[] = {

	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) },
@@ -117,7 +122,7 @@ static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx) 
	 * when PF writes to MBOX(1), in next revisions when

	 * PF writes to MBOX(0)

	 */

	if (nic->rev_id == 0) {

	if (pass1_silicon(nic)) {

		/* see the comment for nic_reg_write()/nic_reg_read()

		 * functions above

		 */
@@ -305,9 +310,6 @@ static void nic_init_hw(struct nicpf *nic) 
{

	int i;



	/* Reset NIC, in case the driver is repeatedly inserted and removed */

	nic_reg_write(nic, NIC_PF_SOFT_RESET, 1);



	/* Enable NIC HW block */

	nic_reg_write(nic, NIC_PF_CFG, 0x3);
@@ -395,8 +397,18 @@ static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg) 
			padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */



		/* Leave RSS_SIZE as '0' to disable RSS */

		if (pass1_silicon(nic)) {

			nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),

				      (vnic << 24) | (padd << 16) |

				      (rssi_base + rssi));

		} else {

			/* Set MPI_ALG to '0' to disable MCAM parsing */

			nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),

			      (vnic << 24) | (padd << 16) | (rssi_base + rssi));

				      (padd << 16));

			/* MPI index is same as CPI if MPI_ALG is not enabled */

			nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3),

				      (vnic << 24) | (rssi_base + rssi));

		}



		if ((rssi + 1) >= cfg->rq_cnt)

			continue;
@@ -409,6 +421,7 @@ static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg) 
			rssi = ((cpi - cpi_base) & 0x38) >> 3;

	}

	nic->cpi_base[cfg->vf_id] = cpi_base;

	nic->rssi_base[cfg->vf_id] = rssi_base;

}



/* Responsds to VF with its RSS indirection table size */
@@ -434,10 +447,9 @@ static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg) 
{

	u8  qset, idx = 0;

	u64 cpi_cfg, cpi_base, rssi_base, rssi;

	u64 idx_addr;



	cpi_base = nic->cpi_base[cfg->vf_id];

	cpi_cfg = nic_reg_read(nic, NIC_PF_CPI_0_2047_CFG | (cpi_base << 3));

	rssi_base = (cpi_cfg & 0x0FFF) + cfg->tbl_offset;

	rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset;



	rssi = rssi_base;

	qset = cfg->vf_id;
@@ -454,9 +466,15 @@ static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg) 
		idx++;

	}



	cpi_base = nic->cpi_base[cfg->vf_id];

	if (pass1_silicon(nic))

		idx_addr = NIC_PF_CPI_0_2047_CFG;

	else

		idx_addr = NIC_PF_MPI_0_2047_CFG;

	cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3));

	cpi_cfg &= ~(0xFULL << 20);

	cpi_cfg |= (cfg->hash_bits << 20);

	nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi_base << 3), cpi_cfg);

	nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg);

}



/* 4 level transmit side scheduler configutation
@@ -1001,8 +1019,6 @@ static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 
		goto err_release_regions;

	}



	pci_read_config_byte(pdev, PCI_REVISION_ID, &nic->rev_id);



	nic->node = nic_get_node_id(pdev);



	nic_set_lmac_vf_mapping(nic);

drivers/net/ethernet/cavium/thunder/nic_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -85,7 +85,11 @@ 
#define   NIC_PF_ECC3_DBE_INT_W1S		(0x2708)

#define   NIC_PF_ECC3_DBE_ENA_W1C		(0x2710)

#define   NIC_PF_ECC3_DBE_ENA_W1S		(0x2718)

#define   NIC_PF_MCAM_0_191_ENA			(0x100000)

#define   NIC_PF_MCAM_0_191_M_0_5_DATA		(0x110000)

#define   NIC_PF_MCAM_CTRL			(0x120000)

#define   NIC_PF_CPI_0_2047_CFG			(0x200000)

#define   NIC_PF_MPI_0_2047_CFG			(0x210000)

#define   NIC_PF_RSSI_0_4097_RQ			(0x220000)

#define   NIC_PF_LMAC_0_7_CFG			(0x240000)

#define   NIC_PF_LMAC_0_7_SW_XOFF		(0x242000)

drivers/net/ethernet/cavium/thunder/nicvf_main.c

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 
static const struct pci_device_id nicvf_id_table[] = {

	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,

			 PCI_DEVICE_ID_THUNDER_NIC_VF,

			 PCI_VENDOR_ID_CAVIUM, 0xA11E) },

			 PCI_VENDOR_ID_CAVIUM, 0xA134) },

	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,

			 PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF,

			 PCI_VENDOR_ID_CAVIUM, 0xA11E) },