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Commit 2a000443 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'qcom-dts-for-4.18' of... 

Merge tag 'qcom-dts-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt

Qualcomm Device Tree Changes for v4.18

* APQ8064 fixes for irq translations and pci address translation
* Fix RPM clock controller compatible on MSM8660
* Add TZ and SMEM reserved regions on IPQ4019
* Add vadc nodes for PM8941
* Disable i2c by default at top level APQ8064 dtsi

* tag 'qcom-dts-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux

:
  ARM: dts: qcom-apq8064: use correct pci address for address translation
  ARM: dts: qcom-apq8064: fix gic_irq_domain_translate warnings
  ARM: dts: Fix the RPM clock controller compatible string
  ARM: dts: ipq4019: Add TZ and SMEM reserved regions
  ARM: dts: qcom: pm8941: Add vadc nodes needed to estimate an ocv
  ARM: dts: qcom-apq8064: disable i2c by default at soc dtsi

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents efe53228 90ce6265

arch/arm/boot/dts/qcom-apq8064.dtsi

+31 −27
Original line number Diff line number Diff line
@@ -444,7 +444,7 @@ 
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";

				reg = <0x12450000 0x100>,

				      <0x12400000 0x03>;

				interrupts = <0 193 0x0>;

				interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;

				clock-names = "core", "iface";

				status = "disabled";
@@ -456,11 +456,12 @@ 
				pinctrl-1 = <&i2c1_pins_sleep>;

				pinctrl-names = "default", "sleep";

				reg = <0x12460000 0x1000>;

				interrupts = <0 194 IRQ_TYPE_NONE>;

				interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;

				clock-names = "core", "iface";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};



		};
@@ -484,11 +485,12 @@ 
				pinctrl-0 = <&i2c2_pins>;

				pinctrl-1 = <&i2c2_pins_sleep>;

				pinctrl-names = "default", "sleep";

				interrupts = <0 196 IRQ_TYPE_NONE>;

				interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;

				clock-names = "core", "iface";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};

		};
@@ -508,12 +510,13 @@ 
				pinctrl-1 = <&i2c3_pins_sleep>;

				pinctrl-names = "default", "sleep";

				reg = <0x16280000 0x1000>;

				interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;

				interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI3_QUP_CLK>,

					 <&gcc GSBI3_H_CLK>;

				clock-names = "core", "iface";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};

		};
@@ -534,10 +537,11 @@ 
				pinctrl-1 = <&i2c4_pins_sleep>;

				pinctrl-names = "default", "sleep";

				reg = <0x16380000 0x1000>;

				interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;

				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI4_QUP_CLK>,

					 <&gcc GSBI4_H_CLK>;

				clock-names = "core", "iface";

				status = "disabled";

			};

		};
@@ -556,7 +560,7 @@ 
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";

				reg = <0x1a240000 0x100>,

				      <0x1a200000 0x03>;

				interrupts = <0 154 0x0>;

				interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;

				clock-names = "core", "iface";

				status = "disabled";
@@ -565,7 +569,7 @@ 
			gsbi5_spi: spi@1a280000 {

				compatible = "qcom,spi-qup-v1.1.1";

				reg = <0x1a280000 0x1000>;

				interrupts = <0 155 0>;

				interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;

				pinctrl-0 = <&spi5_default>;

				pinctrl-1 = <&spi5_sleep>;

				pinctrl-names = "default", "sleep";
@@ -592,7 +596,7 @@ 
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";

				reg = <0x16540000 0x100>,

				      <0x16500000 0x03>;

				interrupts = <0 156 0x0>;

				interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;

				clock-names = "core", "iface";

				status = "disabled";
@@ -604,7 +608,7 @@ 
				pinctrl-1 = <&i2c6_pins_sleep>;

				pinctrl-names = "default", "sleep";

				reg = <0x16580000 0x1000>;

				interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;

				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI6_QUP_CLK>,

					 <&gcc GSBI6_H_CLK>;

				clock-names = "core", "iface";
@@ -628,7 +632,7 @@ 
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";

				reg = <0x16640000 0x1000>,

				      <0x16600000 0x1000>;

				interrupts = <0 158 0x0>;

				interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;

				clock-names = "core", "iface";

				status = "disabled";
@@ -640,7 +644,7 @@ 
				pinctrl-1 = <&i2c7_pins_sleep>;

				pinctrl-names = "default", "sleep";

				reg = <0x16680000 0x1000>;

				interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;

				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI7_QUP_CLK>,

					 <&gcc GSBI7_H_CLK>;

				clock-names = "core", "iface";
@@ -1056,7 +1060,7 @@ 
			compatible		= "qcom,apq8064-ahci", "generic-ahci";

			status			= "disabled";

			reg			= <0x29000000 0x180>;

			interrupts		= <GIC_SPI 209 IRQ_TYPE_NONE>;

			interrupts		= <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;



			clocks			= <&gcc SFAB_SATA_S_H_CLK>,

						<&gcc SATA_H_CLK>,
@@ -1082,7 +1086,7 @@ 
		sdcc1bam:dma@12402000{

			compatible = "qcom,bam-v1.3.0";

			reg = <0x12402000 0x8000>;

			interrupts = <0 98 0>;

			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc SDC1_H_CLK>;

			clock-names = "bam_clk";

			#dma-cells = <1>;
@@ -1092,7 +1096,7 @@ 
		sdcc3bam:dma@12182000{

			compatible = "qcom,bam-v1.3.0";

			reg = <0x12182000 0x8000>;

			interrupts = <0 96 0>;

			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc SDC3_H_CLK>;

			clock-names = "bam_clk";

			#dma-cells = <1>;
@@ -1102,7 +1106,7 @@ 
		sdcc4bam:dma@121c2000{

			compatible = "qcom,bam-v1.3.0";

			reg = <0x121c2000 0x8000>;

			interrupts = <0 95 0>;

			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc SDC4_H_CLK>;

			clock-names = "bam_clk";

			#dma-cells = <1>;
@@ -1181,7 +1185,7 @@ 
			compatible = "qcom,adreno-3xx";

			reg = <0x04300000 0x20000>;

			reg-names = "kgsl_3d0_reg_memory";

			interrupts = <GIC_SPI 80 0>;

			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "kgsl_3d0_irq";

			clock-names =

			    "core_clk",
@@ -1281,7 +1285,7 @@ 
			label = "MDSS DSI CTRL->0";

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <GIC_SPI 82 0>;

			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x04700000 0x200>;

			reg-names = "dsi_ctrl";
@@ -1350,8 +1354,8 @@ 
			    <&mmcc MDP_AXI_CLK>;

			reg = <0x07500000 0x100000>;

			interrupts =

			    <GIC_SPI 63 0>,

			    <GIC_SPI 64 0>;

			    <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,

			    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;

			qcom,ncb = <2>;

		};
@@ -1366,8 +1370,8 @@ 
			    <&mmcc MDP_AXI_CLK>;

			reg = <0x07600000 0x100000>;

			interrupts =

			    <GIC_SPI 61 0>,

			    <GIC_SPI 62 0>;

			    <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,

			    <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

			qcom,ncb = <2>;

		};
@@ -1382,8 +1386,8 @@ 
			    <&mmcc GFX3D_AXI_CLK>;

			reg = <0x07c00000 0x100000>;

			interrupts =

			    <GIC_SPI 69 0>,

			    <GIC_SPI 70 0>;

			    <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,

			    <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;

			qcom,ncb = <3>;

		};
@@ -1398,8 +1402,8 @@ 
			    <&mmcc GFX3D_AXI_CLK>;

			reg = <0x07d00000 0x100000>;

			interrupts =

			    <GIC_SPI 210 0>,

			    <GIC_SPI 211 0>;

			    <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,

			    <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;

			qcom,ncb = <3>;

		};
@@ -1417,8 +1421,8 @@ 
			#address-cells = <3>;

			#size-cells = <2>;

			ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */

				  0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */

			interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;

				  0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */

			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi";

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

arch/arm/boot/dts/qcom-ipq4019.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -23,6 +23,22 @@ 
	compatible = "qcom,ipq4019";

	interrupt-parent = <&intc>;



	reserved-memory {

		#address-cells = <0x1>;

		#size-cells = <0x1>;

		ranges;



		smem_region: smem@87e00000 {

			reg = <0x87e00000 0x080000>;

			no-map;

		};



		tz@87e80000 {

			reg = <0x87e80000 0x180000>;

			no-map;

		};

	};



	aliases {

		spi0 = &spi_0;

		i2c0 = &i2c_0;

arch/arm/boot/dts/qcom-msm8660.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -452,7 +452,7 @@ 
			clock-names = "ram";



			rpmcc: clock-controller {

				compatible	= "qcom,rpmcc-apq8660", "qcom,rpmcc";

				compatible	= "qcom,rpmcc-msm8660", "qcom,rpmcc";

				#clock-cells = <1>;

			};

arch/arm/boot/dts/qcom-pm8941.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -139,6 +139,9 @@ 
			#size-cells = <0>;

			#io-channel-cells = <1>;



			bat_temp {

				reg = <VADC_LR_MUX1_BAT_THERM>;

			};

			die_temp {

				reg = <VADC_DIE_TEMP>;

			};
@@ -154,6 +157,9 @@ 
			ref_vdd {

				reg = <VADC_VDD_VADC>;

			};

			vbat_sns {

				reg = <VADC_VBAT_SNS>;

			};

		};



		pm8941_iadc: iadc@3600 {