Merge tag 'qcom-arm64-for-4.18' of...

Qualcomm Bluetooth Chips

---------------------

This documents the binding structure and common properties for serial

attached Qualcomm devices.

Serial attached Qualcomm devices shall be a child node of the host UART

device the slave device is attached to.

Required properties:

 - compatible: should contain one of the following:

   * "qcom,qca6174-bt"

Optional properties:

 - enable-gpios: gpio specifier used to enable chip

 - clocks: clock provided to the controller (SUSCLK_32KHZ)

Example:

serial@7570000 {

	label = "BT-UART";

	status = "okay";

	bluetooth {

		compatible = "qcom,qca6174-bt";

		enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;

		clocks = <&divclk4>;

	};

};

Command DB

---------

Command DB is a database that provides a mapping between resource key and the

resource address for a system resource managed by a remote processor. The data

is stored in a shared memory region and is loaded by the remote processor.

Some of the Qualcomm Technologies Inc SoC's have hardware accelerators for

controlling shared resources. Depending on the board configuration the shared

resource properties may change. These properties are dynamically probed by the

remote processor and made available in the shared memory.

The bindings for Command DB is specified in the reserved-memory section in

devicetree. The devicetree representation of the command DB driver should be:

Properties:

- compatible:

	Usage: required

	Value type: <string>

	Definition: Should be "qcom,cmd-db"

- reg:

	Usage: required

	Value type: <prop encoded array>

	Definition: The register address that points to the actual location of

		    the Command DB in memory.

Example:

	reserved-memory {

		[...]

		reserved-memory@85fe0000 {

			reg = <0x0 0x85fe0000 0x0 0x20000>;

			compatible = "qcom,cmd-db";

			no-map;

		};

	};

Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller

Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper

is a programmable module for supporting a wide range of serial interfaces

like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial

Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP

Wrapper controller is modeled as a node with zero or more child nodes each

representing a serial engine.

Required properties:

- compatible:		Must be "qcom,geni-se-qup".

- reg:			Must contain QUP register address and length.

- clock-names:		Must contain "m-ahb" and "s-ahb".

- clocks:		AHB clocks needed by the device.

Required properties if child node exists:

- #address-cells: 	Must be <1> for Serial Engine Address

- #size-cells: 		Must be <1> for Serial Engine Address Size

- ranges: 		Must be present

Properties for children:

A GENI based QUP wrapper controller node can contain 0 or more child nodes

representing serial devices.  These serial devices can be a QCOM UART, I2C

controller, SPI controller, or some combination of aforementioned devices.

Please refer below the child node definitions for the supported serial

interface protocols.

Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller

Required properties:

- compatible:		Must be "qcom,geni-i2c".

- reg: 			Must contain QUP register address and length.

- interrupts: 		Must contain I2C interrupt.

- clock-names: 		Must contain "se".

- clocks: 		Serial engine core clock needed by the device.

- #address-cells:	Must be <1> for I2C device address.

- #size-cells:		Must be <0> as I2C addresses have no size component.

Optional property:

- clock-frequency:	Desired I2C bus clock frequency in Hz.

			When missing default to 400000Hz.

Child nodes should conform to I2C bus binding as described in i2c.txt.

Qualcomm Technologies Inc. GENI Serial Engine based UART Controller

Required properties:

- compatible:		Must be "qcom,geni-debug-uart".

- reg: 			Must contain UART register location and length.

- interrupts: 		Must contain UART core interrupts.

- clock-names:		Must contain "se".

- clocks:		Serial engine core clock needed by the device.

Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller

Required properties:

- compatible:		Must contain "qcom,geni-spi".

- reg:			Must contain SPI register location and length.

- interrupts:		Must contain SPI controller interrupts.

- clock-names:		Must contain "se".

- clocks:		Serial engine core clock needed by the device.

- spi-max-frequency:	Specifies maximum SPI clock frequency, units - Hz.

- #address-cells:	Must be <1> to define a chip select address on

			the SPI bus.

- #size-cells:		Must be <0>.

SPI slave nodes must be children of the SPI master node and conform to SPI bus

binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.

Example:

	geniqup@8c0000 {

		compatible = "qcom,geni-se-qup";

		reg = <0x8c0000 0x6000>;

		clock-names = "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		i2c0: i2c@a94000 {

			compatible = "qcom,geni-i2c";

			reg = <0xa94000 0x4000>;

			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "se";

			clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&qup_1_i2c_5_active>;

			pinctrl-1 = <&qup_1_i2c_5_sleep>;

			#address-cells = <1>;

			#size-cells = <0>;

		};

		uart0: serial@a88000 {

			compatible = "qcom,geni-debug-uart";

			reg = <0xa88000 0x7000>;

			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "se";

			clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&qup_1_uart_3_active>;

			pinctrl-1 = <&qup_1_uart_3_sleep>;

		};

		spi0: spi@a84000 {

			compatible = "qcom,geni-spi";

			reg = <0xa84000 0x4000>;

			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "se";

			clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&qup_1_spi_2_active>;

			pinctrl-1 = <&qup_1_spi_2_sleep>;

			spi-max-frequency = <19200000>;

			#address-cells = <1>;

			#size-cells = <0>;

		};

	}

dtb-$(CONFIG_ARCH_QCOM)	+= msm8992-bullhead-rev-101.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= msm8994-angler-rev-101.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= msm8996-mtp.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-mtp.dtb

			drive-strength = <2>;	/* 2 MA */

		};

	};

	blsp1_uart1_default: blsp1_uart1_default {

		mux {

			pins = "gpio41", "gpio42", "gpio43", "gpio44";

			function = "blsp_uart2";

		};

		config {

			pins = "gpio41", "gpio42", "gpio43", "gpio44";

			drive-strength = <16>;

			bias-disable;

		};

	};

	blsp1_uart1_sleep: blsp1_uart1_sleep {

		mux {

			pins = "gpio41", "gpio42", "gpio43", "gpio44";

			function = "gpio";

		};

		config {

			pins = "gpio41", "gpio42", "gpio43", "gpio44";

			drive-strength = <2>;

			bias-disable;

		};

	};

};