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Commit 223f93ed authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'tegra-for-3.17-dt' of... 

Merge tag 'tegra-for-3.17-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

Merge "ARM: tegra: device tree changes for 3.17" from Thierry Reding:

- New board support:
  * Apalis T30
- HDA support for Tegra124 and Venice2
- Display on Medcom Wide and Roth
- GK20A support on Tegra124
- XUSB pad controller for Tegra124 and Jetson TK1
- Various cleanups

This pulls in the for-3.17/fuse-move, for-3.17/dt-cros-ec-kbd and
for-3.17/xusb-padctl branches to resolve dependencies.

Note that the Apalis T30 support has a runtime dependency on the
for-3.17/pcie-regulators branch, so they should preferably be applied
in that order. I didn't merge that branch into this because Apalis T30
support is new, therefore can't regress, and because the dependency
exists only at runtime.

* tag 'tegra-for-3.17-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux

: (28 commits)
  ARM: tegra: roth: add display DT node
  ARM: tegra: Fix typoed ams,ext-control properties
  ARM: tegra: jetson-tk1: Add XUSB pad controller
  ARM: tegra: tegra124: Add XUSB pad controller
  ARM: tegra: add GK20A GPU to Tegra124 DT
  ARM: tegra: of: add GK20A device tree binding
  ARM: tegra: roth: enable input on mmc clock pins
  ARM: tegra: roth: fix unsupported pinmux properties
  ARM: tegra: Migrate Apalis T30 PCIe power supply scheme
  ARM: tegra: tamonten: add the display to the Medcom Wide
  ARM: tegra: tamonten: add the base board regulators
  ARM: tegra: initial support for apalis t30
  ARM: tegra: jetson-tk1: mark eMMC as non-removable
  ARM: tegra: venice2 - Enable HDA
  ARM: tegra: Add Tegra124 HDA support
  ARM: tegra: Add the EC i2c tunnel to tegra124-venice2
  soc/tegra: fuse: fix dummy functions
  soc/tegra: fuse: move APB DMA into Tegra20 fuse driver
  soc/tegra: Add efuse and apbmisc bindings
  soc/tegra: Add efuse driver for Tegra
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 58cd070a 2236927d

Documentation/ABI/testing/sysfs-driver-tegra-fuse

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What:		/sys/devices/*/<our-device>/fuse

Date:		February 2014

Contact:	Peter De Schrijver <pdeschrijver@nvidia.com>

Description:	read-only access to the efuses on Tegra20, Tegra30, Tegra114

		and Tegra124 SoC's from NVIDIA. The efuses contain write once

		data programmed at the factory. The data is layed out in 32bit

		words in LSB first format. Each bit represents a single value

		as decoded from the fuse registers. Bits order/assignment

		exactly matches the HW registers, including any unused bits.

Users:		any user space application which wants to read the efuses on

		Tegra SoC's

Documentation/devicetree/bindings/arm/tegra.txt

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@@ -30,6 +30,8 @@ board-specific compatible values: 
  nvidia,seaboard

  nvidia,ventana

  nvidia,whistler

  toradex,apalis_t30

  toradex,apalis_t30-eval

  toradex,colibri_t20-512

  toradex,iris

Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt

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NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.



Required properties:

- compatible : should be:

	"nvidia,tegra20-efuse"

	"nvidia,tegra30-efuse"

	"nvidia,tegra114-efuse"

	"nvidia,tegra124-efuse"

  Details:

  nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data

	due to a hardware bug. Tegra20 also lacks certain information which is

	available in later generations such as fab code, lot code, wafer id,..

  nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:

	The differences between these SoCs are the size of the efuse array,

	the location of the spare (OEM programmable) bits and the location of

	the speedo data.

- reg: Should contain 1 entry: the entry gives the physical address and length

       of the fuse registers.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - fuse

- resets: Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names: Must include the following entries:

 - fuse



Example:



	fuse@7000f800 {

		compatible = "nvidia,tegra20-efuse";

		reg = <0x7000F800 0x400>,

		      <0x70000000 0x400>;

		clocks = <&tegra_car TEGRA20_CLK_FUSE>;

		clock-names = "fuse";

		resets = <&tegra_car 39>;

		reset-names = "fuse";

	};

Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt

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NVIDIA GK20A Graphics Processing Unit



Required properties:

- compatible: "nvidia,<chip>-<gpu>"

  Currently recognized values:

  - nvidia,tegra124-gk20a

- reg: Physical base address and length of the controller's registers.

  Must contain two entries:

  - first entry for bar0

  - second entry for bar1

- interrupts: Must contain an entry for each entry in interrupt-names.

  See ../interrupt-controller/interrupts.txt for details.

- interrupt-names: Must include the following entries:

  - stall

  - nonstall

- vdd-supply: regulator for supply voltage.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - gpu

  - pwr

- resets: Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names: Must include the following entries:

  - gpu



Example:



	gpu@0,57000000 {

		compatible = "nvidia,gk20a";

		reg = <0x0 0x57000000 0x0 0x01000000>,

		      <0x0 0x58000000 0x0 0x01000000>;

		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "stall", "nonstall";

		vdd-supply = <&vdd_gpu>;

		clocks = <&tegra_car TEGRA124_CLK_GPU>,

			 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;

		clock-names = "gpu", "pwr";

		resets = <&tegra_car 184>;

		reset-names = "gpu";

		status = "disabled";

	};

Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt

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NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block



Required properties:

- compatible : should be:

       "nvidia,tegra20-apbmisc"

       "nvidia,tegra30-apbmisc"

       "nvidia,tegra114-apbmisc"

       "nvidia,tegra124-apbmisc"

- reg: Should contain 2 entries: the first entry gives the physical address

       and length of the registers which contain revision and debug features.

       The second entry gives the physical address and length of the

       registers indicating the strapping options.