perf vendor events: Add Silvermont V13 event file

GenuineIntel-6-5E,v24,skylake,core

GenuineIntel-6-8E,v24,skylake,core

GenuineIntel-6-9E,v24,skylake,core

GenuineIntel-6-37,v13,silvermont,core

GenuineIntel-6-4D,v13,silvermont,core

GenuineIntel-6-4C,v13,silvermont,core

[

    {

        "PublicDescription": "This event counts all instruction fetches, not including most uncacheable\r\nfetches.",

        "EventCode": "0x80",

        "Counter": "0,1",

        "UMask": "0x3",

        "EventName": "ICACHE.ACCESSES",

        "SampleAfterValue": "200003",

        "BriefDescription": "Instruction fetches"

    },

    {

        "PublicDescription": "This event counts all instruction fetches from the instruction cache.",

        "EventCode": "0x80",

        "Counter": "0,1",

        "UMask": "0x1",

        "EventName": "ICACHE.HIT",

        "SampleAfterValue": "200003",

        "BriefDescription": "Instruction fetches from Icache"

    },

    {

        "PublicDescription": "This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.",

        "EventCode": "0x80",

        "Counter": "0,1",

        "UMask": "0x2",

        "EventName": "ICACHE.MISSES",

        "SampleAfterValue": "200003",

        "BriefDescription": "Icache miss"

    },

    {

        "PublicDescription": "Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM.  The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine.  Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort.  The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear.  Background: UOPS are produced by two mechanisms.  Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction.  MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition.  This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions.",

        "EventCode": "0xE7",

        "Counter": "0,1",

        "UMask": "0x1",

        "EventName": "MS_DECODED.MS_ENTRY",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts the number of times entered into a ucode flow in the FEC.  Includes inserted flows due to front-end detected faults or assists.  Speculative count."

    },

    {

        "PublicDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction.",

        "EventCode": "0xE9",

        "Counter": "0,1",

        "UMask": "0x1",

        "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction"

    }

]

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[

    {

        "PublicDescription": "This event counts the number of times that pipeline was cleared due to memory ordering issues.",

        "EventCode": "0xC3",

        "Counter": "0,1",

        "UMask": "0x2",

        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

        "SampleAfterValue": "200003",

        "BriefDescription": "Stalls due to Memory ordering"

    }

]

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