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Commit 47cbd67e authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Add Skylake V24 event file 



Add a Intel event file for perf.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-h6mjvfxcyfx2w4pf22xb3e8d@git.kernel.org


[ Lowercased the directory and file names ]
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent d8c30385

tools/perf/pmu-events/arch/x86/mapfile.csv

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@@ -21,3 +21,7 @@ GenuineIntel-6-1E,v2,nehalemep,core 
GenuineIntel-6-1F,v2,nehalemep,core

GenuineIntel-6-1A,v2,nehalemep,core

GenuineIntel-6-2E,v2,nehalemex,core

GenuineIntel-6-4E,v24,skylake,core

GenuineIntel-6-5E,v24,skylake,core

GenuineIntel-6-8E,v24,skylake,core

GenuineIntel-6-9E,v24,skylake,core

tools/perf/pmu-events/arch/x86/skylake/cache.json

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tools/perf/pmu-events/arch/x86/skylake/floating-point.json

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[

    {

        "EventCode": "0xC7",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC7",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC7",

        "Counter": "0,1,2,3",

        "UMask": "0x4",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "EventCode": "0xC7",

        "Counter": "0,1,2,3",

        "UMask": "0x8",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC7",

        "Counter": "0,1,2,3",

        "UMask": "0x10",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "EventCode": "0xC7",

        "Counter": "0,1,2,3",

        "UMask": "0x20",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    },

    {

        "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",

        "EventCode": "0xCA",

        "Counter": "0,1,2,3",

        "UMask": "0x1e",

        "EventName": "FP_ASSIST.ANY",

        "SampleAfterValue": "100003",

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "CounterMask": "1",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

    }

]
 
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tools/perf/pmu-events/arch/x86/skylake/frontend.json

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tools/perf/pmu-events/arch/x86/skylake/memory.json

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