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Commit 0fc7e746 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'mtd/for-4.16' of git://git.infradead.org/linux-mtd

Pull MTD updates from Boris Brezillon:
 "MTD core changes:
   - Rework core functions to avoid duplicating generic checks in
     NAND/OneNAND sub-layers
   - Update the MAINTAINERS entry to reflect the fact that MTD
     maintainers now use a single git tree

  MTD driver changes:
   - CFI: use macros instead of inline functions to limit stack usage
     and make KASAN happy

  NAND core changes:
   - Fix NAND_CMD_NONE handling in nand_command[_lp]() hooks
   - Introduce the ->exec_op() infrastructure
   - Rework NAND buffers handling
   - Fix ECC requirements for K9F4G08U0D
   - Fix nand_do_read_oob() to return the number of bitflips
   - Mark K9F1G08U0E as not supporting subpage writes

  NAND driver changes:
   - MTK: Rework the driver to support new IP versions
   - OMAP OneNAND: Full rework to use new APIs (libgpio, dmaengine) and
     fix DT support
   - Marvell: Add a new driver to replace the pxa3xx one

  SPI NOR core changes:
   - Add support to new ISSI and Cypress/Spansion memory parts.
   - Fix support of Micron memories by checking error bits in the FSR.
   - Fix update of block-protection bits by reading back the SR.
   - Restore the internal state of the SPI flash memory when removing
     the device.

  SPI NOR driver changes:
   - Maintenance for Freescale, Intel and Metiatek drivers.
   - Add support of the direct access mode for the Cadence QSPI
     controller"

* tag 'mtd/for-4.16' of git://git.infradead.org/linux-mtd: (93 commits)
  mtd: nand: sunxi: Fix ECC strength choice
  mtd: nand: gpmi: Fix subpage reads
  mtd: nand: Fix build issues due to an anonymous union
  mtd: nand: marvell: Fix missing memory allocation modifier
  mtd: nand: marvell: remove redundant variable 'oob_len'
  mtd: nand: marvell: fix spelling mistake: "suceed"-> "succeed"
  mtd: onenand: omap2: Remove redundant dev_err call in omap2_onenand_probe()
  mtd: Remove duplicate checks on mtd_oob_ops parameter
  mtd: Fallback to ->_read/write_oob() when ->_read/write() is missing
  mtd: mtdpart: Make ECC stat handling consistent
  mtd: onenand: omap2: print resource using %pR format string
  mtd: mtk-nor: modify functions' name more generally
  mtd: onenand: samsung: remove incorrect __iomem annotation
  MAINTAINERS: Add entry for Marvell NAND controller driver
  ARM: OMAP2+: Remove gpmc-onenand
  mtd: onenand: omap2: Configure driver from DT
  mtd: onenand: omap2: Decouple DMA enabling from INT pin availability
  mtd: onenand: omap2: Do not make delay for GPIO OMAP3 specific
  mtd: onenand: omap2: Convert to use dmaengine for memcpy
  mtd: onenand: omap2: Unify OMAP2 and OMAP3 DMA implementation
  ...
parents aa5e75bc 571cb17b
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+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ Required properties:
  - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
  - interrupts : Should contain the interrupt for the device
  - clocks : The clocks needed by the QuadSPI controller
  - clock-names : the name of the clocks
  - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi".

Optional properties:
  - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B.
+4 −2
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@@ -9,13 +9,14 @@ Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt

Required properties:

 - compatible:		"ti,omap2-onenand"
 - reg:			The CS line the peripheral is connected to
 - gpmc,device-width	Width of the ONENAND device connected to the GPMC
 - gpmc,device-width:	Width of the ONENAND device connected to the GPMC
			in bytes. Must be 1 or 2.

Optional properties:

 - dma-channel:		DMA Channel index
 - int-gpios:		GPIO specifier for the INT pin.

For inline partition table parsing (optional):

@@ -35,6 +36,7 @@ Example for an OMAP3430 board:
		#size-cells = <1>;

		onenand@0 {
			compatible = "ti,omap2-onenand";
			reg = <0 0 0>; /* CS0, offset 0 */
			gpmc,device-width = <2>;

+123 −0
Original line number Diff line number Diff line
Marvell NAND Flash Controller (NFC)

Required properties:
- compatible: can be one of the following:
    * "marvell,armada-8k-nand-controller"
    * "marvell,armada370-nand-controller"
    * "marvell,pxa3xx-nand-controller"
    * "marvell,armada-8k-nand" (deprecated)
    * "marvell,armada370-nand" (deprecated)
    * "marvell,pxa3xx-nand" (deprecated)
  Compatibles marked deprecated support only the old bindings described
  at the bottom.
- reg: NAND flash controller memory area.
- #address-cells: shall be set to 1. Encode the NAND CS.
- #size-cells: shall be set to 0.
- interrupts: shall define the NAND controller interrupt.
- clocks: shall reference the NAND controller clock.
- marvell,system-controller: Set to retrieve the syscon node that handles
  NAND controller related registers (only required with the
  "marvell,armada-8k-nand[-controller]" compatibles).

Optional properties:
- label: see partition.txt. New platforms shall omit this property.
- dmas: shall reference DMA channel associated to the NAND controller.
  This property is only used with "marvell,pxa3xx-nand[-controller]"
  compatible strings.
- dma-names: shall be "rxtx".
  This property is only used with "marvell,pxa3xx-nand[-controller]"
  compatible strings.

Optional children nodes:
Children nodes represent the available NAND chips.

Required properties:
- reg: shall contain the native Chip Select ids (0-3).
- nand-rb: see nand.txt (0-1).

Optional properties:
- marvell,nand-keep-config: orders the driver not to take the timings
  from the core and leaving them completely untouched. Bootloader
  timings will then be used.
- label: MTD name.
- nand-on-flash-bbt: see nand.txt.
- nand-ecc-mode: see nand.txt. Will use hardware ECC if not specified.
- nand-ecc-algo: see nand.txt. This property is essentially useful when
  not using hardware ECC. Howerver, it may be added when using hardware
  ECC for clarification but will be ignored by the driver because ECC
  mode is chosen depending on the page size and the strength required by
  the NAND chip. This value may be overwritten with nand-ecc-strength
  property.
- nand-ecc-strength: see nand.txt.
- nand-ecc-step-size: see nand.txt. Marvell's NAND flash controller does
  use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
  step size will shrink or grow in order to fit the required strength.
  Step sizes are not completely random for all and follow certain
  patterns described in AN-379, "Marvell SoC NFC ECC".

See Documentation/devicetree/bindings/mtd/nand.txt for more details on
generic bindings.


Example:
nand_controller: nand-controller@d0000 {
	compatible = "marvell,armada370-nand-controller";
	reg = <0xd0000 0x54>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&coredivclk 0>;

	nand@0 {
		reg = <0>;
		label = "main-storage";
		nand-rb = <0>;
		nand-ecc-mode = "hw";
		marvell,nand-keep-config;
		nand-on-flash-bbt;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "Rootfs";
				reg = <0x00000000 0x40000000>;
			};
		};
	};
};


Note on legacy bindings: One can find, in not-updated device trees,
bindings slightly different than described above with other properties
described below as well as the partitions node at the root of a so
called "nand" node (without clear controller/chip separation).

Legacy properties:
- marvell,nand-enable-arbiter: To enable the arbiter, all boards blindly
  used it, this bit was set by the bootloader for many boards and even if
  it is marked reserved in several datasheets, it might be needed to set
  it (otherwise it is harmless) so whether or not this property is set,
  the bit is selected by the driver.
- num-cs: Number of chip-select lines to use, all boards blindly set 1
  to this and for a reason, other values would have failed. The value of
  this property is ignored.

Example:

	nand0: nand@43100000 {
		compatible = "marvell,pxa3xx-nand";
		reg = <0x43100000 90>;
		interrupts = <45>;
		dmas = <&pdma 97 0>;
		dma-names = "rxtx";
		#address-cells = <1>;
		marvell,nand-keep-config;
		marvell,nand-enable-arbiter;
		num-cs = <1>;
		/* Partitions (optional) */
       };
+8 −3
Original line number Diff line number Diff line
@@ -12,8 +12,10 @@ tree nodes.

The first part of NFC is NAND Controller Interface (NFI) HW.
Required NFI properties:
- compatible:			Should be one of "mediatek,mt2701-nfc",
				"mediatek,mt2712-nfc".
- compatible:			Should be one of
				"mediatek,mt2701-nfc",
				"mediatek,mt2712-nfc",
				"mediatek,mt7622-nfc".
- reg:				Base physical address and size of NFI.
- interrupts:			Interrupts of NFI.
- clocks:			NFI required clocks.
@@ -142,7 +144,10 @@ Example:
==============

Required BCH properties:
- compatible:	Should be one of "mediatek,mt2701-ecc", "mediatek,mt2712-ecc".
- compatible:	Should be one of
		"mediatek,mt2701-ecc",
		"mediatek,mt2712-ecc",
		"mediatek,mt7622-ecc".
- reg:		Base physical address and size of ECC.
- interrupts:	Interrupts of ECC.
- clocks:	ECC required clocks.
+1 −0
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@@ -43,6 +43,7 @@ Optional NAND chip properties:
		     This is particularly useful when only the in-band area is
		     used by the upper layers, and you want to make your NAND
		     as reliable as possible.
- nand-rb: shall contain the native Ready/Busy ids.

The ECC strength and ECC step size properties define the correction capability
of a controller. Together, they say a controller can correct "{strength} bit
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