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Commit 098e5303 authored by Jerome Brunet's avatar Jerome Brunet Committed by Kevin Hilman
Browse files

ARM64: dts: meson: add MMC resets 



Add reset lines to the mmc controllers of the meson gx and axg SoCs

Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent 5e395e14

arch/arm64/boot/dts/amlogic/meson-axg.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/axg-clkc.h>

#include <dt-bindings/gpio/meson-axg-gpio.h>

#include <dt-bindings/reset/amlogic,meson-axg-reset.h>



/ {

	compatible = "amlogic,meson-axg";
@@ -137,6 +138,7 @@ 
					<&clkc CLKID_SD_EMMC_B_CLK0>,

					<&clkc CLKID_FCLK_DIV2>;

				clock-names = "core", "clkin0", "clkin1";

				resets = <&reset RESET_SD_EMMC_B>;

			};



			sd_emmc_c: mmc@7000 {
@@ -148,6 +150,7 @@ 
					<&clkc CLKID_SD_EMMC_C_CLK0>,

					<&clkc CLKID_FCLK_DIV2>;

				clock-names = "core", "clkin0", "clkin1";

				resets = <&reset RESET_SD_EMMC_C>;

			};

		};

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -715,6 +715,7 @@ 
		 <&clkc CLKID_SD_EMMC_A_CLK0>,

		 <&clkc CLKID_FCLK_DIV2>;

	clock-names = "core", "clkin0", "clkin1";

	resets = <&reset RESET_SD_EMMC_A>;

};



&sd_emmc_b {
@@ -722,6 +723,7 @@ 
		 <&clkc CLKID_SD_EMMC_B_CLK0>,

		 <&clkc CLKID_FCLK_DIV2>;

	clock-names = "core", "clkin0", "clkin1";

	resets = <&reset RESET_SD_EMMC_B>;

};



&sd_emmc_c {
@@ -729,6 +731,7 @@ 
		 <&clkc CLKID_SD_EMMC_C_CLK0>,

		 <&clkc CLKID_FCLK_DIV2>;

	clock-names = "core", "clkin0", "clkin1";

	resets = <&reset RESET_SD_EMMC_C>;

};



&spicc {

arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

+4 −1
Original line number Diff line number Diff line
@@ -724,6 +724,7 @@ 
		 <&clkc CLKID_SD_EMMC_A_CLK0>,

		 <&clkc CLKID_FCLK_DIV2>;

	clock-names = "core", "clkin0", "clkin1";

	resets = <&reset RESET_SD_EMMC_A>;

};



&sd_emmc_b {
@@ -731,6 +732,7 @@ 
		 <&clkc CLKID_SD_EMMC_B_CLK0>,

		 <&clkc CLKID_FCLK_DIV2>;

	clock-names = "core", "clkin0", "clkin1";

	resets = <&reset RESET_SD_EMMC_B>;

};



&sd_emmc_c {
@@ -738,6 +740,7 @@ 
		 <&clkc CLKID_SD_EMMC_C_CLK0>,

		 <&clkc CLKID_FCLK_DIV2>;

	clock-names = "core", "clkin0", "clkin1";

	resets = <&reset RESET_SD_EMMC_C>;

};



&spicc {