Commit 5e395e14 authored Mar 28, 2018 by Yixun Lan Committed by Kevin Hilman May 09, 2018

ARM64: dts: meson-axg: add an 32K alt aoclk



The ao_clk81 in AO domain have two clock source,
one from a 32K alt crystal we name it as ao_alt_clk,
another is the clk81 signal from EE domain.

Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

parent 0df8fbb9

arch/arm64/boot/dts/amlogic/meson-axg.dtsi

+7 −0

Original line number	Diff line number	Diff line
		@@ -108,6 +108,13 @@
		#clock-cells = <0>;
		};

		ao_alt_xtal: ao_alt_xtal-clk {
		compatible = "fixed-clock";
		clock-frequency = <32000000>;
		clock-output-names = "ao_alt_xtal";
		#clock-cells = <0>;
		};

		soc {
		compatible = "simple-bus";
		#address-cells = <2>;