Commit 0904deaf authored Jun 12, 2015 by Mika Kahola Committed by Daniel Vetter Jun 15, 2015

drm/i915: Limit CHV max cdclk



Limit CHV maximum cdclk to 320MHz.

v2: Rebase to the latest
v3: Clean up of if-else tree

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent d8514d63

drivers/gpu/drm/i915/intel_display.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -5271,6 +5271,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
		dev_priv->max_cdclk_freq = 540000;
		else
		dev_priv->max_cdclk_freq = 675000;
		} else if (IS_CHERRYVIEW(dev)) {
		dev_priv->max_cdclk_freq = 320000;
		} else if (IS_VALLEYVIEW(dev)) {
		dev_priv->max_cdclk_freq = 400000;
		} else {