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Commit d8514d63 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
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drm/i915: don't set the FBC plane select bits on HSW+ 



This commit is just to make the intentions explicit: on HSW+ these
bits are MBZ, but since we only support plane A and the macro
evaluates to zero when plane A is the parameter, we're not fixing any
bug.

v2:
 - Remove useless extra blank like (Chris).
 - Init dpfc_ctl in another place (Chris).

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 2e8144a5

drivers/gpu/drm/i915/intel_fbc.c

+4 −1
Original line number Diff line number Diff line
@@ -262,7 +262,10 @@ static void gen7_fbc_enable(struct drm_crtc *crtc) 


	dev_priv->fbc.enabled = true;



	dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);

	dpfc_ctl = 0;

	if (IS_IVYBRIDGE(dev))

		dpfc_ctl |= IVB_DPFC_CTL_PLANE(intel_crtc->plane);



	if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)

		dev_priv->fbc.threshold++;