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Commit 086b2882 authored by Bin Liu's avatar Bin Liu Committed by Greg Kroah-Hartman
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usb: musb: dsps: use musb register read/write wrappers instead 



musb core already exports the register read/write wrappers, so clean up
the duplication in dsps glue.

Signed-off-by: default avatarBin Liu <b-liu@ti.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent b99d3659

drivers/usb/musb/musb_dsps.c

+44 −68
Original line number Diff line number Diff line
@@ -51,30 +51,6 @@ 


static const struct of_device_id musb_dsps_of_match[];



/**

 * avoid using musb_readx()/musb_writex() as glue layer should not be

 * dependent on musb core layer symbols.

 */

static inline u8 dsps_readb(const void __iomem *addr, unsigned offset)

{

	return __raw_readb(addr + offset);

}



static inline u32 dsps_readl(const void __iomem *addr, unsigned offset)

{

	return __raw_readl(addr + offset);

}



static inline void dsps_writeb(void __iomem *addr, unsigned offset, u8 data)

{

	__raw_writeb(data, addr + offset);

}



static inline void dsps_writel(void __iomem *addr, unsigned offset, u32 data)

{

	__raw_writel(data, addr + offset);

}



/**

 * DSPS musb wrapper register offset.

 * FIXME: This should be expanded to have all the wrapper registers from TI DSPS
@@ -223,8 +199,8 @@ static void dsps_musb_enable(struct musb *musb) 
	       ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);

	coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);



	dsps_writel(reg_base, wrp->epintr_set, epmask);

	dsps_writel(reg_base, wrp->coreintr_set, coremask);

	musb_writel(reg_base, wrp->epintr_set, epmask);

	musb_writel(reg_base, wrp->coreintr_set, coremask);

	/* start polling for ID change in dual-role idle mode */

	if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&

			musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
@@ -244,10 +220,10 @@ static void dsps_musb_disable(struct musb *musb) 
	const struct dsps_musb_wrapper *wrp = glue->wrp;

	void __iomem *reg_base = musb->ctrl_base;



	dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);

	dsps_writel(reg_base, wrp->epintr_clear,

	musb_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);

	musb_writel(reg_base, wrp->epintr_clear,

			 wrp->txep_bitmap | wrp->rxep_bitmap);

	dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);

	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);

}



static void otg_timer(unsigned long _musb)
@@ -265,14 +241,14 @@ static void otg_timer(unsigned long _musb) 
	 * We poll because DSPS IP's won't expose several OTG-critical

	 * status change events (from the transceiver) otherwise.

	 */

	devctl = dsps_readb(mregs, MUSB_DEVCTL);

	devctl = musb_readb(mregs, MUSB_DEVCTL);

	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,

				usb_otg_state_string(musb->xceiv->otg->state));



	spin_lock_irqsave(&musb->lock, flags);

	switch (musb->xceiv->otg->state) {

	case OTG_STATE_A_WAIT_BCON:

		dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);

		musb_writeb(musb->mregs, MUSB_DEVCTL, 0);

		skip_session = 1;

		/* fall */
@@ -286,13 +262,13 @@ static void otg_timer(unsigned long _musb) 
			MUSB_HST_MODE(musb);

		}

		if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session)

			dsps_writeb(mregs, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);

			musb_writeb(mregs, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);

		mod_timer(&glue->timer, jiffies +

				msecs_to_jiffies(wrp->poll_timeout));

		break;

	case OTG_STATE_A_WAIT_VFALL:

		musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;

		dsps_writel(musb->ctrl_base, wrp->coreintr_set,

		musb_writel(musb->ctrl_base, wrp->coreintr_set,

			    MUSB_INTR_VBUSERROR << wrp->usb_shift);

		break;

	default:
@@ -315,29 +291,29 @@ static irqreturn_t dsps_interrupt(int irq, void *hci) 
	spin_lock_irqsave(&musb->lock, flags);



	/* Get endpoint interrupts */

	epintr = dsps_readl(reg_base, wrp->epintr_status);

	epintr = musb_readl(reg_base, wrp->epintr_status);

	musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;

	musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;



	if (epintr)

		dsps_writel(reg_base, wrp->epintr_status, epintr);

		musb_writel(reg_base, wrp->epintr_status, epintr);



	/* Get usb core interrupts */

	usbintr = dsps_readl(reg_base, wrp->coreintr_status);

	usbintr = musb_readl(reg_base, wrp->coreintr_status);

	if (!usbintr && !epintr)

		goto out;



	musb->int_usb =	(usbintr & wrp->usb_bitmap) >> wrp->usb_shift;

	if (usbintr)

		dsps_writel(reg_base, wrp->coreintr_status, usbintr);

		musb_writel(reg_base, wrp->coreintr_status, usbintr);



	dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",

			usbintr, epintr);



	if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {

		int drvvbus = dsps_readl(reg_base, wrp->status);

		int drvvbus = musb_readl(reg_base, wrp->status);

		void __iomem *mregs = musb->mregs;

		u8 devctl = dsps_readb(mregs, MUSB_DEVCTL);

		u8 devctl = musb_readb(mregs, MUSB_DEVCTL);

		int err;



		err = musb->int_usb & MUSB_INTR_VBUSERROR;
@@ -442,7 +418,7 @@ static int dsps_musb_init(struct musb *musb) 
	musb->phy = devm_phy_get(dev->parent, "usb2-phy");



	/* Returns zero if e.g. not clocked */

	rev = dsps_readl(reg_base, wrp->revision);

	rev = musb_readl(reg_base, wrp->revision);

	if (!rev)

		return -ENODEV;
@@ -463,14 +439,14 @@ static int dsps_musb_init(struct musb *musb) 
	setup_timer(&glue->timer, otg_timer, (unsigned long) musb);



	/* Reset the musb */

	dsps_writel(reg_base, wrp->control, (1 << wrp->reset));

	musb_writel(reg_base, wrp->control, (1 << wrp->reset));



	musb->isr = dsps_interrupt;



	/* reset the otgdisable bit, needed for host mode to work */

	val = dsps_readl(reg_base, wrp->phy_utmi);

	val = musb_readl(reg_base, wrp->phy_utmi);

	val &= ~(1 << wrp->otg_disable);

	dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);

	musb_writel(musb->ctrl_base, wrp->phy_utmi, val);



	/*

	 *  Check whether the dsps version has babble control enabled.
@@ -478,11 +454,11 @@ static int dsps_musb_init(struct musb *musb) 
	 * If MUSB_BABBLE_CTL returns 0x4 then we have the babble control

	 * logic enabled.

	 */

	val = dsps_readb(musb->mregs, MUSB_BABBLE_CTL);

	val = musb_readb(musb->mregs, MUSB_BABBLE_CTL);

	if (val & MUSB_BABBLE_RCV_DISABLE) {

		glue->sw_babble_enabled = true;

		val |= MUSB_BABBLE_SW_SESSION_CTRL;

		dsps_writeb(musb->mregs, MUSB_BABBLE_CTL, val);

		musb_writeb(musb->mregs, MUSB_BABBLE_CTL, val);

	}



	return dsps_musb_dbg_init(musb, glue);
@@ -510,7 +486,7 @@ static int dsps_musb_set_mode(struct musb *musb, u8 mode) 
	void __iomem *ctrl_base = musb->ctrl_base;

	u32 reg;



	reg = dsps_readl(ctrl_base, wrp->mode);

	reg = musb_readl(ctrl_base, wrp->mode);



	switch (mode) {

	case MUSB_HOST:
@@ -523,8 +499,8 @@ static int dsps_musb_set_mode(struct musb *musb, u8 mode) 
		 */

		reg |= (1 << wrp->iddig_mux);



		dsps_writel(ctrl_base, wrp->mode, reg);

		dsps_writel(ctrl_base, wrp->phy_utmi, 0x02);

		musb_writel(ctrl_base, wrp->mode, reg);

		musb_writel(ctrl_base, wrp->phy_utmi, 0x02);

		break;

	case MUSB_PERIPHERAL:

		reg |= (1 << wrp->iddig);
@@ -536,10 +512,10 @@ static int dsps_musb_set_mode(struct musb *musb, u8 mode) 
		 */

		reg |= (1 << wrp->iddig_mux);



		dsps_writel(ctrl_base, wrp->mode, reg);

		musb_writel(ctrl_base, wrp->mode, reg);

		break;

	case MUSB_OTG:

		dsps_writel(ctrl_base, wrp->phy_utmi, 0x02);

		musb_writel(ctrl_base, wrp->phy_utmi, 0x02);

		break;

	default:

		dev_err(glue->dev, "unsupported mode %d\n", mode);
@@ -554,7 +530,7 @@ static bool dsps_sw_babble_control(struct musb *musb) 
	u8 babble_ctl;

	bool session_restart =  false;



	babble_ctl = dsps_readb(musb->mregs, MUSB_BABBLE_CTL);

	babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);

	dev_dbg(musb->controller, "babble: MUSB_BABBLE_CTL value %x\n",

		babble_ctl);

	/*
@@ -571,14 +547,14 @@ static bool dsps_sw_babble_control(struct musb *musb) 
		 * babble is due to noise, then set transmit idle (d7 bit)

		 * to resume normal operation

		 */

		babble_ctl = dsps_readb(musb->mregs, MUSB_BABBLE_CTL);

		babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);

		babble_ctl |= MUSB_BABBLE_FORCE_TXIDLE;

		dsps_writeb(musb->mregs, MUSB_BABBLE_CTL, babble_ctl);

		musb_writeb(musb->mregs, MUSB_BABBLE_CTL, babble_ctl);



		/* wait till line monitor flag cleared */

		dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n");

		do {

			babble_ctl = dsps_readb(musb->mregs, MUSB_BABBLE_CTL);

			babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);

			udelay(1);

		} while ((babble_ctl & MUSB_BABBLE_STUCK_J) && timeout--);
@@ -896,13 +872,13 @@ static int dsps_suspend(struct device *dev) 
		return 0;



	mbase = musb->ctrl_base;

	glue->context.control = dsps_readl(mbase, wrp->control);

	glue->context.epintr = dsps_readl(mbase, wrp->epintr_set);

	glue->context.coreintr = dsps_readl(mbase, wrp->coreintr_set);

	glue->context.phy_utmi = dsps_readl(mbase, wrp->phy_utmi);

	glue->context.mode = dsps_readl(mbase, wrp->mode);

	glue->context.tx_mode = dsps_readl(mbase, wrp->tx_mode);

	glue->context.rx_mode = dsps_readl(mbase, wrp->rx_mode);

	glue->context.control = musb_readl(mbase, wrp->control);

	glue->context.epintr = musb_readl(mbase, wrp->epintr_set);

	glue->context.coreintr = musb_readl(mbase, wrp->coreintr_set);

	glue->context.phy_utmi = musb_readl(mbase, wrp->phy_utmi);

	glue->context.mode = musb_readl(mbase, wrp->mode);

	glue->context.tx_mode = musb_readl(mbase, wrp->tx_mode);

	glue->context.rx_mode = musb_readl(mbase, wrp->rx_mode);



	return 0;

}
@@ -918,13 +894,13 @@ static int dsps_resume(struct device *dev) 
		return 0;



	mbase = musb->ctrl_base;

	dsps_writel(mbase, wrp->control, glue->context.control);

	dsps_writel(mbase, wrp->epintr_set, glue->context.epintr);

	dsps_writel(mbase, wrp->coreintr_set, glue->context.coreintr);

	dsps_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi);

	dsps_writel(mbase, wrp->mode, glue->context.mode);

	dsps_writel(mbase, wrp->tx_mode, glue->context.tx_mode);

	dsps_writel(mbase, wrp->rx_mode, glue->context.rx_mode);

	musb_writel(mbase, wrp->control, glue->context.control);

	musb_writel(mbase, wrp->epintr_set, glue->context.epintr);

	musb_writel(mbase, wrp->coreintr_set, glue->context.coreintr);

	musb_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi);

	musb_writel(mbase, wrp->mode, glue->context.mode);

	musb_writel(mbase, wrp->tx_mode, glue->context.tx_mode);

	musb_writel(mbase, wrp->rx_mode, glue->context.rx_mode);

	if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&

	    musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)

		mod_timer(&glue->timer, jiffies +