Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 05359be1 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
Browse files

clk: sunxi-ng: Add driver for A83T CCU 



The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.

Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.

Also, the MMC2 module clock supports switching to a "new timing" mode.
This mode divides the clock output by half, and disables the CCU based
clock delays. The MMC controller must be configure to the same mode,
and then use its internal clock delays.

This driver does not support runtime switching of the timing modes.
Instead, the new timing mode is enforced at probe time. Consumers can
check which mode is active by trying to get the current phase delay
of the MMC2 phase clocks, which will return -ENOTSUPP if the new
timing mode is active.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 13e0dde8

drivers/clk/sunxi-ng/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -116,6 +116,17 @@ config SUN8I_A33_CCU 
	default MACH_SUN8I

	depends on MACH_SUN8I || COMPILE_TEST



config SUN8I_A83T_CCU

	bool "Support for the Allwinner A83T CCU"

	select SUNXI_CCU_DIV

	select SUNXI_CCU_GATE

	select SUNXI_CCU_MP

	select SUNXI_CCU_MUX

	select SUNXI_CCU_NKMP

	select SUNXI_CCU_NM

	select SUNXI_CCU_PHASE

	default MACH_SUN8I



config SUN8I_H3_CCU

	bool "Support for the Allwinner H3 CCU"

	select SUNXI_CCU_DIV

drivers/clk/sunxi-ng/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o 
obj-$(CONFIG_SUN6I_A31_CCU)	+= ccu-sun6i-a31.o

obj-$(CONFIG_SUN8I_A23_CCU)	+= ccu-sun8i-a23.o

obj-$(CONFIG_SUN8I_A33_CCU)	+= ccu-sun8i-a33.o

obj-$(CONFIG_SUN8I_A83T_CCU)	+= ccu-sun8i-a83t.o

obj-$(CONFIG_SUN8I_H3_CCU)	+= ccu-sun8i-h3.o

obj-$(CONFIG_SUN8I_V3S_CCU)	+= ccu-sun8i-v3s.o

obj-$(CONFIG_SUN8I_DE2_CCU)	+= ccu-sun8i-de2.o

drivers/clk/sunxi-ng/ccu-sun8i-a83t.c

0 → 100644
+922 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/sunxi-ng/ccu-sun8i-a83t.h

0 → 100644
+64 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2016 Chen-Yu Tsai

 *

 * Chen-Yu Tsai <wens@csie.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _CCU_SUN8I_A83T_H_

#define _CCU_SUN8I_A83T_H_



#include <dt-bindings/clock/sun8i-a83t-ccu.h>

#include <dt-bindings/reset/sun8i-a83t-ccu.h>



#define CLK_PLL_C0CPUX		0

#define CLK_PLL_C1CPUX		1

#define CLK_PLL_AUDIO		2

#define CLK_PLL_VIDEO0		3

#define CLK_PLL_VE		4

#define CLK_PLL_DDR		5



/* pll-periph is exported to the PRCM block */



#define CLK_PLL_GPU		7

#define CLK_PLL_HSIC		8



/* pll-de is exported for the display engine */



#define CLK_PLL_VIDEO1		10



/* The CPUX clocks are exported */



#define CLK_AXI0		13

#define CLK_AXI1		14

#define CLK_AHB1		15

#define CLK_AHB2		16

#define CLK_APB1		17

#define CLK_APB2		18



/* bus gates exported */



#define CLK_CCI400		58



/* module and usb clocks exported */



#define CLK_DRAM		82



/* dram gates and more module clocks exported */



#define CLK_MBUS		95



/* more module clocks exported */



#define CLK_NUMBER		(CLK_GPU_HYD + 1)



#endif /* _CCU_SUN8I_A83T_H_ */

include/dt-bindings/clock/sun8i-a83t-ccu.h

0 → 100644
+140 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>

 *

 * This file is dual-licensed: you can use it either under the terms

 * of the GPL or the X11 license, at your option. Note that this dual

 * licensing only applies to this file, and not this project as a

 * whole.

 *

 *  a) This file is free software; you can redistribute it and/or

 *     modify it under the terms of the GNU General Public License as

 *     published by the Free Software Foundation; either version 2 of the

 *     License, or (at your option) any later version.

 *

 *     This file is distributed in the hope that it will be useful,

 *     but WITHOUT ANY WARRANTY; without even the implied warranty of

 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 *     GNU General Public License for more details.

 *

 * Or, alternatively,

 *

 *  b) Permission is hereby granted, free of charge, to any person

 *     obtaining a copy of this software and associated documentation

 *     files (the "Software"), to deal in the Software without

 *     restriction, including without limitation the rights to use,

 *     copy, modify, merge, publish, distribute, sublicense, and/or

 *     sell copies of the Software, and to permit persons to whom the

 *     Software is furnished to do so, subject to the following

 *     conditions:

 *

 *     The above copyright notice and this permission notice shall be

 *     included in all copies or substantial portions of the Software.

 *

 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES

 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 *     OTHER DEALINGS IN THE SOFTWARE.

 */



#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_

#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_



#define CLK_PLL_PERIPH		6



#define CLK_PLL_DE		9



#define CLK_C0CPUX		11

#define CLK_C1CPUX		12



#define CLK_BUS_MIPI_DSI	19

#define CLK_BUS_SS		20

#define CLK_BUS_DMA		21

#define CLK_BUS_MMC0		22

#define CLK_BUS_MMC1		23

#define CLK_BUS_MMC2		24

#define CLK_BUS_NAND		25

#define CLK_BUS_DRAM		26

#define CLK_BUS_EMAC		27

#define CLK_BUS_HSTIMER		28

#define CLK_BUS_SPI0		29

#define CLK_BUS_SPI1		30

#define CLK_BUS_OTG		31

#define CLK_BUS_EHCI0		32

#define CLK_BUS_EHCI1		33

#define CLK_BUS_OHCI0		34



#define CLK_BUS_VE		35

#define CLK_BUS_TCON0		36

#define CLK_BUS_TCON1		37

#define CLK_BUS_CSI		38

#define CLK_BUS_HDMI		39

#define CLK_BUS_DE		40

#define CLK_BUS_GPU		41

#define CLK_BUS_MSGBOX		42

#define CLK_BUS_SPINLOCK	43



#define CLK_BUS_SPDIF		44

#define CLK_BUS_PIO		45

#define CLK_BUS_I2S0		46

#define CLK_BUS_I2S1		47

#define CLK_BUS_I2S2		48

#define CLK_BUS_TDM		49



#define CLK_BUS_I2C0		50

#define CLK_BUS_I2C1		51

#define CLK_BUS_I2C2		52

#define CLK_BUS_UART0		53

#define CLK_BUS_UART1		54

#define CLK_BUS_UART2		55

#define CLK_BUS_UART3		56

#define CLK_BUS_UART4		57



#define CLK_NAND		59

#define CLK_MMC0		60

#define CLK_MMC0_SAMPLE		61

#define CLK_MMC0_OUTPUT		62

#define CLK_MMC1		63

#define CLK_MMC1_SAMPLE		64

#define CLK_MMC1_OUTPUT		65

#define CLK_MMC2		66

#define CLK_MMC2_SAMPLE		67

#define CLK_MMC2_OUTPUT		68

#define CLK_SS			69

#define CLK_SPI0		70

#define CLK_SPI1		71

#define CLK_I2S0		72

#define CLK_I2S1		73

#define CLK_I2S2		74

#define CLK_TDM			75

#define CLK_SPDIF		76

#define CLK_USB_PHY0		77

#define CLK_USB_PHY1		78

#define CLK_USB_HSIC		79

#define CLK_USB_HSIC_12M	80

#define CLK_USB_OHCI0		81



#define CLK_DRAM_VE		83

#define CLK_DRAM_CSI		84



#define CLK_TCON0		85

#define CLK_TCON1		86

#define CLK_CSI_MISC		87

#define CLK_MIPI_CSI		88

#define CLK_CSI_MCLK		89

#define CLK_CSI_SCLK		90

#define CLK_VE			91

#define CLK_AVS			92

#define CLK_HDMI		93

#define CLK_HDMI_SLOW		94



#define CLK_MIPI_DSI0		96

#define CLK_MIPI_DSI1		97

#define CLK_GPU_CORE		98

#define CLK_GPU_MEMORY		99

#define CLK_GPU_HYD		100



#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */