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Commit 019c5beb authored by Kevin Hilman's avatar Kevin Hilman
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Merge tag 'for-kevin-meson-clk-bindings-v4.18-1' of... 

Merge tag 'for-kevin-meson-clk-bindings-v4.18-1' of https://github.com/BayLibre/clk-meson into v4.18/dt64

First round of binding update for meson clocks targeted at v4.18

# gpg: Signature made Wed May 16 01:23:15 2018 PDT
# gpg:                using RSA key F4E159AE18F3F56D5F1BB71BE6FC0F1C37F2DA85
# gpg: Can't check signature: No public key

* tag 'for-kevin-meson-clk-bindings-v4.18-1' of https://github.com/BayLibre/clk-meson:
  dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
  dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
  clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
  dt-bindings: clock: meson8b: export the NAND clock
parents ffe2f2a4 9c7aea8e

Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt

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Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ Required Properties: 
	- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"

	- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"

	- GXM (S912) : "amlogic,meson-gxm-aoclkc"

	- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"

	followed by the common "amlogic,meson-gx-aoclkc"



- #clock-cells: should be 1.

include/dt-bindings/clock/axg-aoclkc.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */

/*

 * Copyright (c) 2016 BayLibre, SAS

 * Author: Neil Armstrong <narmstrong@baylibre.com>

 *

 * Copyright (c) 2018 Amlogic, inc.

 * Author: Qiufang Dai <qiufang.dai@amlogic.com>

 */



#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK

#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK



#define CLKID_AO_REMOTE		0

#define CLKID_AO_I2C_MASTER	1

#define CLKID_AO_I2C_SLAVE	2

#define CLKID_AO_UART1		3

#define CLKID_AO_UART2		4

#define CLKID_AO_IR_BLASTER	5

#define CLKID_AO_SAR_ADC	6

#define CLKID_AO_CLK81		7

#define CLKID_AO_SAR_ADC_SEL	8

#define CLKID_AO_SAR_ADC_DIV	9

#define CLKID_AO_SAR_ADC_CLK	10

#define CLKID_AO_ALT_XTAL	11



#endif

include/dt-bindings/clock/gxbb-clkc.h

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@@ -125,5 +125,7 @@ 
#define CLKID_VAPB_1		138

#define CLKID_VAPB_SEL		139

#define CLKID_VAPB		140

#define CLKID_VDEC_1		153

#define CLKID_VDEC_HEVC		156



#endif /* __GXBB_CLKC_H */

include/dt-bindings/clock/meson8b-clkc.h

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Original line number Diff line number Diff line
@@ -102,5 +102,6 @@ 
#define CLKID_MPLL0		93

#define CLKID_MPLL1		94

#define CLKID_MPLL2		95

#define CLKID_NAND_CLK		112



#endif /* __MESON8B_CLKC_H */

include/dt-bindings/reset/axg-aoclkc.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */

/*

 * Copyright (c) 2016 BayLibre, SAS

 * Author: Neil Armstrong <narmstrong@baylibre.com>

 *

 * Copyright (c) 2018 Amlogic, inc.

 * Author: Qiufang Dai <qiufang.dai@amlogic.com>

 */



#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK

#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK



#define RESET_AO_REMOTE		0

#define RESET_AO_I2C_MASTER	1

#define RESET_AO_I2C_SLAVE	2

#define RESET_AO_UART1		3

#define RESET_AO_UART2		4

#define RESET_AO_IR_BLASTER	5



#endif