Commit fff367c7 authored Oct 27, 2012 by Daniel Vetter

drm/i915: clarify why we need to enable fdi plls so early



For reference, see "Graphics BSpec: vol4g North Display Engine
Registers [IVB], Display Mode Set Sequence", step 4 of the enabling
sequence:

a. "Enable PCH FDI Receiver PLL, wait for warmup plus DMI latency
b. "Switch from Rawclk to PCDclk in FDI Receiver
c. "Enable CPU FDI Transmitter PLL, wait for warmup"

Cc: Paulo Zanoni <przanoni@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent cd986abb

drivers/gpu/drm/i915/intel_display.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -3227,6 +3227,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
		is_pch_port = ironlake_crtc_driving_pch(crtc);

		if (is_pch_port) {
		/* Note: FDI PLL enabling _must_ be done before we enable the
		* cpu pipes, hence this is separate from all the other fdi/pch
		* enabling. */
		ironlake_fdi_pll_enable(intel_crtc);
		} else {
		assert_fdi_tx_disabled(dev_priv, pipe);