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Commit cd986abb authored by Daniel Vetter's avatar Daniel Vetter
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drm/i915: Write the FDI RX TU size reg at the right time 



According to "Graphics BSpec: vol4g North Display Engine Registers [IVB],
Display Mode Set Sequence" We need to write the TU size register
of the fdi RX unit _before_ starting to train the link.

Note: The current code is actually correct as Paulo mentioned in
review, but it's a bit confusion since only the fdi rx/tx plls need to
be enabled before the cpu pipes/planes. Hence it's still a good idea
to move the TU_SIZE setting to the "right" spot in the sequence, to
better match Bspec.

Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4a0833ec

drivers/gpu/drm/i915/intel_display.c

+5 −3
Original line number Diff line number Diff line
@@ -2700,9 +2700,6 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) 
	int pipe = intel_crtc->pipe;

	u32 reg, temp;



	/* Write the TU size bits so error detection works */

	I915_WRITE(FDI_RX_TUSIZE1(pipe),

		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);



	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */

	reg = FDI_RX_CTL(pipe);
@@ -3003,6 +3000,11 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) 


	assert_transcoder_disabled(dev_priv, pipe);



	/* Write the TU size bits before fdi link training, so that error

	 * detection works. */

	I915_WRITE(FDI_RX_TUSIZE1(pipe),

		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);



	/* For PCH output, training FDI link */

	dev_priv->display.fdi_link_train(crtc);