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Commit fd392b60 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
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ddrm/i915/bdw: Disable centroid pixel perf optimization 



BDW-A workaround

BDW Bug #1899532

v2: WARN on when not using preliminary HW support

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuosugeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4afe8d33

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -5007,6 +5007,9 @@ 
#define HSW_ROW_CHICKEN3		0xe49c

#define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)



#define HALF_SLICE_CHICKEN3		0xe184

#define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)



#define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)

#define INTEL_AUDIO_DEVCL		0x808629FB

#define INTEL_AUDIO_DEVBLC		0x80862801

drivers/gpu/drm/i915/intel_pm.c

+4 −0
Original line number Diff line number Diff line
@@ -5286,6 +5286,10 @@ static void gen8_init_clock_gating(struct drm_device *dev) 
	/* FIXME(BDW): Check all the w/a, some might only apply to

	 * pre-production hw. */



	WARN(!i915_preliminary_hw_support,

	     "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");

	I915_WRITE(HALF_SLICE_CHICKEN3,

		   _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));

	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));



	/* WaSwitchSolVfFArbitrationPriority */