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Commit 4afe8d33 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915/bdw: BWGTLB clock gate disable 



Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuosugeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent fe4ab3ce

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -660,6 +660,7 @@ 
#define   ARB_MODE_SWIZZLE_SNB	(1<<4)

#define   ARB_MODE_SWIZZLE_IVB	(1<<5)

#define GAMTARBMODE		0x04a08

#define   ARB_MODE_BWGTLB_DISABLE (1<<9)

#define   ARB_MODE_SWIZZLE_BDW	(1<<1)

#define RENDER_HWS_PGA_GEN7	(0x04080)

#define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)

drivers/gpu/drm/i915/intel_pm.c

+2 −0
Original line number Diff line number Diff line
@@ -5286,6 +5286,8 @@ static void gen8_init_clock_gating(struct drm_device *dev) 
	/* FIXME(BDW): Check all the w/a, some might only apply to

	 * pre-production hw. */



	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));



	/* WaSwitchSolVfFArbitrationPriority */

	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);