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Commit f2032f24 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Olof Johansson
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ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes 



This SoC is integrated with 4 Cortex-A9 cores.  The GIC bindings
document says that the bits[15:8] of the 3rd cell of the interrupts
property represents PPI interrupt CPU mask.  Because the timer
interrupts are wired to all of the 4 cores, bits[15:8] should be set
to 0xf.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 62060a35

arch/arm/boot/dts/uniphier-proxstream2.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -249,14 +249,14 @@ 
		timer@60000200 {

			compatible = "arm,cortex-a9-global-timer";

			reg = <0x60000200 0x20>;

			interrupts = <1 11 0x304>;

			interrupts = <1 11 0xf04>;

			clocks = <&arm_timer_clk>;

		};



		timer@60000600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0x60000600 0x20>;

			interrupts = <1 13 0x304>;

			interrupts = <1 13 0xf04>;

			clocks = <&arm_timer_clk>;

		};