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Commit 62060a35 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'omap-for-v4.3/dt-pt4-v2' of... 

Merge tag 'omap-for-v4.3/dt-pt4-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt

Fix up bogus RTC compatible change for am4372 and add missing
DPLL for am4372 cpsw Ethernet driver. Also add ARM global and
local timers for am4372.

* tag 'omap-for-v4.3/dt-pt4-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap

:
  arm: boot: dts: am4372: add ARM timers and SCU nodes
  ARM: dts: AM4372: Add the am4372-rtc compatible string
  ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk clock
  ARM: dts: AM437X: add dpll_clksel_mac_clk node

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 582271a3 8cbd4c2f

Documentation/devicetree/bindings/rtc/rtc-omap.txt

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ Required properties: 
			    Wakeup generation for event Alarm. It can also be

			    used to control an external PMIC via the

			    pmic_power_en pin.

	- "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.

- reg: Address range of rtc register set

- interrupts: rtc timer, alarm interrupts in order

- interrupt-parent: phandle for the interrupt controller

arch/arm/boot/dts/am4372.dtsi

+28 −3
Original line number Diff line number Diff line
@@ -64,6 +64,27 @@ 
		interrupt-parent = <&gic>;

	};



	scu: scu@48240000 {

		compatible = "arm,cortex-a9-scu";

		reg = <0x48240000 0x100>;

	};



	global_timer: timer@48240200 {

		compatible = "arm,cortex-a9-global-timer";

		reg = <0x48240200 0x100>;

		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gic>;

		clocks = <&dpll_mpu_m2_ck>;

	};



	local_timer: timer@48240600 {

		compatible = "arm,cortex-a9-twd-timer";

		reg = <0x48240600 0x100>;

		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gic>;

		clocks = <&dpll_mpu_m2_ck>;

	};



	l2-cache-controller@48242000 {

		compatible = "arm,pl310-cache";

		reg = <0x48242000 0x1000>;
@@ -330,7 +351,8 @@ 
		};



		rtc: rtc@44e3e000 {

			compatible = "ti,am3352-rtc", "ti,da830-rtc";

			compatible = "ti,am4372-rtc", "ti,am3352-rtc",

				     "ti,da830-rtc";

			reg = <0x44e3e000 0x1000>;

			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -549,8 +571,11 @@ 
			#address-cells = <1>;

			#size-cells = <1>;

			ti,hwmods = "cpgmac0";

			clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;

			clock-names = "fck", "cpts";

			clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,

				 <&dpll_clksel_mac_clk>;

			clock-names = "fck", "cpts", "50mclk";

			assigned-clocks = <&dpll_clksel_mac_clk>;

			assigned-clock-rates = <50000000>;

			status = "disabled";

			cpdma_channels = <8>;

			ale_entries = <1024>;

arch/arm/boot/dts/am43xx-clocks.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -486,6 +486,15 @@ 
		reg = <0x4238>;

	};



	dpll_clksel_mac_clk: dpll_clksel_mac_clk {

		#clock-cells = <0>;

		compatible = "ti,divider-clock";

		clocks = <&dpll_core_m5_ck>;

		reg = <0x4234>;

		ti,bit-shift = <2>;

		ti,dividers = <2>, <5>;

	};



	clk_32k_mosc_ck: clk_32k_mosc_ck {

		#clock-cells = <0>;

		compatible = "fixed-clock";

drivers/clk/ti/clk-43xx.c

+1 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ static struct ti_dt_clk am43xx_clks[] = { 
	DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),

	DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),

	DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),

	DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"),

	DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),

	DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),

	DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),