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Commit 582271a3 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'renesas-dt4-for-v4.3' of... 

Merge tag 'renesas-dt4-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Fourth Round of Renesas ARM Based SoC DT Updates for v4.3

* Enable Clock Domain support of the Clock Pulse Generator (CPG)
  Module Stop (MSTP) Clocks driver.

* tag 'renesas-dt4-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

:
  ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
  clk: shmobile: rz: Add CPG/MSTP Clock Domain support
  clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
  clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
  clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
  clk: shmobile: Add CPG/MSTP Clock Domain support

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 3cf6a067 60c0745a

Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt

+26 −3
Original line number Diff line number Diff line 
* Renesas R8A7778 Clock Pulse Generator (CPG)



The CPG generates core clocks for the R8A7778. It includes two PLLs and

several fixed ratio dividers

several fixed ratio dividers.

The CPG also provides a Clock Domain for SoC devices, in combination with the

CPG Module Stop (MSTP) Clocks.



Required Properties:
@@ -10,10 +12,18 @@ Required Properties: 
  - #clock-cells: Must be 1

  - clock-output-names: The names of the clocks. Supported clocks are

    "plla", "pllb", "b", "out", "p", "s", and "s1".

  - #power-domain-cells: Must be 0



SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed

through an MSTP clock should refer to the CPG device node in their

"power-domains" property, as documented by the generic PM domain bindings in

Documentation/devicetree/bindings/power/power_domain.txt.



Example

-------



Examples

--------



  - CPG device node:



	cpg_clocks: cpg_clocks@ffc80000 {

		compatible = "renesas,r8a7778-cpg-clocks";
@@ -22,4 +32,17 @@ Example 
		clocks = <&extal_clk>;

		clock-output-names = "plla", "pllb", "b",

				     "out", "p", "s", "s1";

		#power-domain-cells = <0>;

	};





  - CPG/MSTP Clock Domain member device node:



	sdhi0: sd@ffe4c000 {

		compatible = "renesas,sdhi-r8a7778";

		reg = <0xffe4c000 0x100>;

		interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};

Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt

+26 −4
Original line number Diff line number Diff line 
* Renesas R8A7779 Clock Pulse Generator (CPG)



The CPG generates core clocks for the R8A7779. It includes one PLL and

several fixed ratio dividers

several fixed ratio dividers.

The CPG also provides a Clock Domain for SoC devices, in combination with the

CPG Module Stop (MSTP) Clocks.



Required Properties:
@@ -12,16 +14,36 @@ Required Properties: 
  - #clock-cells: Must be 1

  - clock-output-names: The names of the clocks. Supported clocks are "plla",

    "z", "zs", "s", "s1", "p", "b", "out".

  - #power-domain-cells: Must be 0



SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed

through an MSTP clock should refer to the CPG device node in their

"power-domains" property, as documented by the generic PM domain bindings in

Documentation/devicetree/bindings/power/power_domain.txt.



Example

-------



Examples

--------



  - CPG device node:



	cpg_clocks: cpg_clocks@ffc80000 {

		compatible = "renesas,r8a7779-cpg-clocks";

		reg = <0 0xffc80000 0 0x30>;

		reg = <0xffc80000 0x30>;

		clocks = <&extal_clk>;

		#clock-cells = <1>;

		clock-output-names = "plla", "z", "zs", "s", "s1", "p",

		                     "b", "out";

		#power-domain-cells = <0>;

	};





  - CPG/MSTP Clock Domain member device node:



	sata: sata@fc600000 {

		compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";

		reg = <0xfc600000 0x2000>;

		interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp1_clks R8A7779_CLK_SATA>;

		power-domains = <&cpg_clocks>;

	};

Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt

+24 −2
Original line number Diff line number Diff line
@@ -2,6 +2,8 @@ 


The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs

and several fixed ratio dividers.

The CPG also provides a Clock Domain for SoC devices, in combination with the

CPG Module Stop (MSTP) Clocks.



Required Properties:
@@ -20,10 +22,18 @@ Required Properties: 
  - clock-output-names: The names of the clocks. Supported clocks are "main",

    "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and

    "adsp"

  - #power-domain-cells: Must be 0



SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed

through an MSTP clock should refer to the CPG device node in their

"power-domains" property, as documented by the generic PM domain bindings in

Documentation/devicetree/bindings/power/power_domain.txt.



Example

-------



Examples

--------



  - CPG device node:



	cpg_clocks: cpg_clocks@e6150000 {

		compatible = "renesas,r8a7790-cpg-clocks",
@@ -34,4 +44,16 @@ Example 
		clock-output-names = "main", "pll0, "pll1", "pll3",

				     "lb", "qspi", "sdh", "sd0", "sd1", "z",

				     "rcan", "adsp";

		#power-domain-cells = <0>;

	};





  - CPG/MSTP Clock Domain member device node:



	thermal@e61f0000 {

		compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";

		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;

		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;

		power-domains = <&cpg_clocks>;

	};

Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt

+27 −2
Original line number Diff line number Diff line
@@ -2,6 +2,8 @@ 


The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable

CPU and GPU clocks, and several fixed ratio dividers.

The CPG also provides a Clock Domain for SoC devices, in combination with the

CPG Module Stop (MSTP) Clocks.



Required Properties:
@@ -14,10 +16,18 @@ Required Properties: 
  - #clock-cells: Must be 1

  - clock-output-names: The names of the clocks. Supported clocks are "pll",

    "i", and "g"

  - #power-domain-cells: Must be 0



SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed

through an MSTP clock should refer to the CPG device node in their

"power-domains" property, as documented by the generic PM domain bindings in

Documentation/devicetree/bindings/power/power_domain.txt.



Example

-------



Examples

--------



  - CPG device node:



	cpg_clocks: cpg_clocks@fcfe0000 {

		#clock-cells = <1>;
@@ -26,4 +36,19 @@ Example 
		reg = <0xfcfe0000 0x18>;

		clocks = <&extal_clk>, <&usb_x1_clk>;

		clock-output-names = "pll", "i", "g";

		#power-domain-cells = <0>;

	};





  - CPG/MSTP Clock Domain member device node:



	mtu2: timer@fcff0000 {

		compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";

		reg = <0xfcff0000 0x400>;

		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "tgi0a";

		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;

		clock-names = "fck";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};

arch/arm/boot/dts/r7s72100.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ 
			reg = <0xfcfe0000 0x18>;

			clocks = <&extal_clk>, <&usb_x1_clk>;

			clock-output-names = "pll", "i", "g";

			#power-domain-cells = <0>;

		};



		/* MSTP clocks */
@@ -157,6 +158,7 @@ 
			     <0 189 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -169,6 +171,7 @@ 
			     <0 193 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -181,6 +184,7 @@ 
			     <0 197 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -193,6 +197,7 @@ 
			     <0 201 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -205,6 +210,7 @@ 
			     <0 205 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -217,6 +223,7 @@ 
			     <0 209 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -229,6 +236,7 @@ 
			     <0 213 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -241,6 +249,7 @@ 
			     <0 217 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -252,6 +261,7 @@ 
			     <0 240 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI0>;

		power-domains = <&cpg_clocks>;

		num-cs = <1>;

		#address-cells = <1>;

		#size-cells = <0>;
@@ -266,6 +276,7 @@ 
			     <0 243 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI1>;

		power-domains = <&cpg_clocks>;

		num-cs = <1>;

		#address-cells = <1>;

		#size-cells = <0>;
@@ -280,6 +291,7 @@ 
			     <0 246 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI2>;

		power-domains = <&cpg_clocks>;

		num-cs = <1>;

		#address-cells = <1>;

		#size-cells = <0>;
@@ -294,6 +306,7 @@ 
			     <0 249 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI3>;

		power-domains = <&cpg_clocks>;

		num-cs = <1>;

		#address-cells = <1>;

		#size-cells = <0>;
@@ -308,6 +321,7 @@ 
			     <0 252 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI4>;

		power-domains = <&cpg_clocks>;

		num-cs = <1>;

		#address-cells = <1>;

		#size-cells = <0>;
@@ -338,6 +352,7 @@ 
			     <0 164 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C0>;

		clock-frequency = <100000>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -356,6 +371,7 @@ 
			     <0 172 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C1>;

		clock-frequency = <100000>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -374,6 +390,7 @@ 
			     <0 180 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C2>;

		clock-frequency = <100000>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -392,6 +409,7 @@ 
			     <0 188 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C3>;

		clock-frequency = <100000>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};
@@ -402,6 +420,7 @@ 
		interrupt-names = "tgi0a";

		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;

		clock-names = "fck";

		power-domains = <&cpg_clocks>;

		status = "disabled";

	};

};