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Commit f12d0d7c authored by Hyok S. Choi's avatar Hyok S. Choi Committed by Russell King
Browse files

[ARM] nommu: manage the CP15 things 



All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:

     Related operation	Safe condition
  a. any CP15 access	!CPU_CP15
  b. alignment trap	CPU_CP15_MMU
  c. D-cache(C-bit)	CPU_CP15
  d. I-cache		CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
				CPU_ARM720 || CPU_ARM740 ||
				CPU_XSCALE || CPU_XSC3 )
  e. alternate vector	CPU_CP15 && !CPU_ARM740
  f. TTB		CPU_CP15_MMU
  g. Domain		CPU_CP15_MMU
  h. FSR/FAR		CPU_CP15_MMU

For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.

Signed-off-by: default avatarHyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent fefdaa06

arch/arm/Kconfig

+2 −1
Original line number Diff line number Diff line
@@ -621,6 +621,7 @@ config LEDS_CPU 


config ALIGNMENT_TRAP

	bool

	depends on CPU_CP15_MMU

	default y if !ARCH_EBSA110

	help

	  ARM processors can not fetch/store information which is not
@@ -852,7 +853,7 @@ source "drivers/base/Kconfig" 


source "drivers/connector/Kconfig"



if ALIGNMENT_TRAP

if ALIGNMENT_TRAP || !CPU_CP15_MMU

source "drivers/mtd/Kconfig"

endif

arch/arm/Kconfig-nommu

+8 −0
Original line number Diff line number Diff line
@@ -25,6 +25,14 @@ config FLASH_SIZE 
	hex 'FLASH Size' if SET_MEM_PARAM

	default 0x00400000



config PROCESSOR_ID

	hex

	default 0x00007700

	depends on !CPU_CP15

	help

	  If processor has no CP15 register, this processor ID is

	  used instead of the auto-probing which utilizes the register.



config REMAP_VECTORS_TO_RAM

	bool 'Install vectors to the begining of RAM' if DRAM_BASE

	depends on DRAM_BASE

arch/arm/boot/compressed/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -51,7 +51,11 @@ OBJS += head-at91rm9200.o 
endif



ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)

ifeq ($(CONFIG_CPU_CP15),y)

OBJS		+= big-endian.o

else

# The endian should be set by h/w design.

endif

endif



#

arch/arm/boot/compressed/head.S

+6 −0
Original line number Diff line number Diff line
@@ -82,9 +82,11 @@ 
		kphex	r6, 8		/* processor id */

		kputc	#':'

		kphex	r7, 8		/* architecture id */

#ifdef CONFIG_CPU_CP15

		kputc	#':'

		mrc	p15, 0, r0, c1, c0

		kphex	r0, 8		/* control reg */

#endif

		kputc	#'\n'

		kphex	r5, 8		/* decompressed kernel start */

		kputc	#'-'
@@ -507,7 +509,11 @@ call_kernel: bl cache_clean_flush 
 */



call_cache_fn:	adr	r12, proc_types

#ifdef CONFIG_CPU_CP15

		mrc	p15, 0, r6, c0, c0	@ get processor ID

#else

		ldr	r6, =CONFIG_PROCESSOR_ID

#endif

1:		ldr	r1, [r12, #0]		@ get value

		ldr	r2, [r12, #4]		@ get mask

		eor	r1, r1, r6		@ (real ^ match)

arch/arm/kernel/head-nommu.S

+6 −1
Original line number Diff line number Diff line
@@ -9,7 +9,6 @@ 
 * published by the Free Software Foundation.

 *

 *  Common kernel startup code (non-paged MM)

 *    for 32-bit CPUs which has a process ID register(CP15).

 *

 */

#include <linux/linkage.h>
@@ -40,7 +39,11 @@ 
ENTRY(stext)

	msr	cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode

						@ and irqs disabled

#ifndef CONFIG_CPU_CP15

	ldr	r9, =CONFIG_PROCESSOR_ID

#else

	mrc	p15, 0, r9, c0, c0		@ get processor id

#endif

	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid

	movs	r10, r5				@ invalid processor (r5=0)?

	beq	__error_p				@ yes, error 'p'
@@ -58,6 +61,7 @@ ENTRY(stext) 
 */

	.type	__after_proc_init, %function

__after_proc_init:

#ifdef CONFIG_CPU_CP15

	mrc	p15, 0, r0, c1, c0, 0		@ read control reg

#ifdef CONFIG_ALIGNMENT_TRAP

	orr	r0, r0, #CR_A
@@ -74,6 +78,7 @@ __after_proc_init: 
	bic	r0, r0, #CR_I

#endif

	mcr	p15, 0, r0, c1, c0, 0		@ write control reg

#endif /* CONFIG_CPU_CP15 */



	mov	pc, r13				@ clear the BSS and jump

						@ to start_kernel