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Commit fefdaa06 authored by Hyok S. Choi's avatar Hyok S. Choi Committed by Russell King
Browse files

[ARM] nommu: defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU 



By merging of uClinux/ARM, we need to treat various CPU cores which have
MMU, MPU or even none for memory management. The memory management
coprocessors are controlled by CP15 register set and the ARM core family
can be categorized by 5 groups by the register ;
  G-a. CP15 is MMU : 610, 710, 720, 920, 922, 925, 926, 1020, 1020e, 1022,
		v6 and the derivations sa1100, sa110, xscale, xsc3.
  G-b. CP15 is MPU : 740, 940, 946, 996, 1156.
  G-c. CP15 is MPU or MMU : 1026 (selectable by schematic design)
  G-d. CP15 is exist, but nothing for memory managemnt : 966, 968.
  G-e. no-CP15 : 7tdmi, 9tdmi, 9e, 9ej

This patch defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU. Thus the
family can be defined as :
  - CPU_CP15 only : G-d
  - CPU_CP15_MMU(implies CPU_CP15) : G-a, G-c(selectable)
  - CPU_CP15_MPU(implies CPU_CP15) : G-b, G-c(selectable)
  - !CPU_CP15 : G-e

Signed-off-by: default avatarHyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 6a570b28

arch/arm/mm/Kconfig

+33 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ config CPU_ARM610 
	select CPU_32v3

	select CPU_CACHE_V3

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V3 if MMU

	select CPU_TLB_V3 if MMU

	help
@@ -31,6 +32,7 @@ config CPU_ARM710 
	select CPU_32v3

	select CPU_CACHE_V3

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V3 if MMU

	select CPU_TLB_V3 if MMU

	help
@@ -50,6 +52,7 @@ config CPU_ARM720T 
	select CPU_ABRT_LV4T

	select CPU_CACHE_V4

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WT if MMU

	select CPU_TLB_V4WT if MMU

	help
@@ -68,6 +71,7 @@ config CPU_ARM920T 
	select CPU_ABRT_EV4T

	select CPU_CACHE_V4WT

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WB if MMU

	select CPU_TLB_V4WBI if MMU

	help
@@ -89,6 +93,7 @@ config CPU_ARM922T 
	select CPU_ABRT_EV4T

	select CPU_CACHE_V4WT

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WB if MMU

	select CPU_TLB_V4WBI if MMU

	help
@@ -108,6 +113,7 @@ config CPU_ARM925T 
	select CPU_ABRT_EV4T

	select CPU_CACHE_V4WT

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WB if MMU

	select CPU_TLB_V4WBI if MMU

 	help
@@ -126,6 +132,7 @@ config CPU_ARM926T 
	select CPU_32v5

	select CPU_ABRT_EV5TJ

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WB if MMU

	select CPU_TLB_V4WBI if MMU

	help
@@ -144,6 +151,7 @@ config CPU_ARM1020 
	select CPU_ABRT_EV4T

	select CPU_CACHE_V4WT

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WB if MMU

	select CPU_TLB_V4WBI if MMU

	help
@@ -161,6 +169,7 @@ config CPU_ARM1020E 
	select CPU_ABRT_EV4T

	select CPU_CACHE_V4WT

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WB if MMU

	select CPU_TLB_V4WBI if MMU

	depends on n
@@ -172,6 +181,7 @@ config CPU_ARM1022 
	select CPU_32v5

	select CPU_ABRT_EV4T

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WB if MMU # can probably do better

	select CPU_TLB_V4WBI if MMU

	help
@@ -189,6 +199,7 @@ config CPU_ARM1026 
	select CPU_32v5

	select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WB if MMU # can probably do better

	select CPU_TLB_V4WBI if MMU

	help
@@ -207,6 +218,7 @@ config CPU_SA110 
	select CPU_ABRT_EV4

	select CPU_CACHE_V4WB

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_COPY_V4WB if MMU

	select CPU_TLB_V4WB if MMU

	help
@@ -227,6 +239,7 @@ config CPU_SA1100 
	select CPU_ABRT_EV4

	select CPU_CACHE_V4WB

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_TLB_V4WB if MMU



# XScale
@@ -237,6 +250,7 @@ config CPU_XSCALE 
	select CPU_32v5

	select CPU_ABRT_EV5T

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_TLB_V4WBI if MMU



# XScale Core Version 3
@@ -247,6 +261,7 @@ config CPU_XSC3 
	select CPU_32v5

	select CPU_ABRT_EV5T

	select CPU_CACHE_VIVT

	select CPU_CP15_MMU

	select CPU_TLB_V4WBI if MMU

	select IO_36
@@ -258,6 +273,7 @@ config CPU_V6 
	select CPU_ABRT_EV6

	select CPU_CACHE_V6

	select CPU_CACHE_VIPT

	select CPU_CP15_MMU

	select CPU_COPY_V6 if MMU

	select CPU_TLB_V6 if MMU
@@ -380,6 +396,23 @@ config CPU_TLB_V6 


endif



config CPU_CP15

	bool

	help

	  Processor has the CP15 register.



config CPU_CP15_MMU

	bool

	select CPU_CP15

	help

	  Processor has the CP15 register, which has MMU related registers.



config CPU_CP15_MPU

	bool

	select CPU_CP15

	help

	  Processor has the CP15 register, which has MPU related registers.



#

# CPU supports 36-bit I/O

#