Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ef39ab79 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branches 'pci/host-designware', 'pci/host-imx6', 'pci/host-keystone',... 

Merge branches 'pci/host-designware', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-tegra' and 'pci/host-xilinx' into next

* pci/host-designware:
  PCI: designware: Fold struct pcie_port_info into struct pcie_port

* pci/host-imx6:
  PCI: imx6: Delay enabling reference clock for SS until it stabilizes

* pci/host-keystone:
  PCI: keystone: Set device ID based on SoC to support multiple ports
  PCI: keystone: Assume controller is already in RC mode
  PCI: keystone: Limit MRSS for all downstream devices

* pci/host-tegra:
  PCI: tegra: Add Tegra124 support
  PCI: tegra: Make sure the PCIe PLL is really reset
  PCI: tegra: Fix extended configuration space mapping
  PCI: tegra: Clear CLKREQ# enable on port disable

* pci/host-xilinx:
  PCI: xilinx: Fix xilinx_pcie_assign_msi() return value test
parents 134cd00d adf70fc0 3fce0e88 8665a482 7f1f054b f9dd0ce6

Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt

+24 −1
Original line number Diff line number Diff line 
NVIDIA Tegra PCIe controller



Required properties:

- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie"

- compatible: Must be one of:

  - "nvidia,tegra20-pcie"

  - "nvidia,tegra30-pcie"

  - "nvidia,tegra124-pcie"

- device_type: Must be "pci"

- reg: A list of physical base address and length for each set of controller

  registers. Must contain an entry for each entry in the reg-names property.
@@ -57,6 +60,11 @@ Required properties: 
  - afi

  - pcie_x



Required properties on Tegra124 and later:

- phys: Must contain an entry for each entry in phy-names.

- phy-names: Must include the following entries:

  - pcie



Power supplies for Tegra20:

- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.

- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
@@ -84,6 +92,21 @@ Power supplies for Tegra30: 
    - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.

    - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.



Power supplies for Tegra124:

- Required:

  - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.

  - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.

  - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must

    supply 1.05 V.

  - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.

    Must supply 3.3 V.

  - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).

    Must supply 3.3 V.

  - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must

    supply 2.8-3.3 V.

  - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must

    supply 1.05 V.



Root ports are defined as subnodes of the PCIe controller node.



Required properties:

Documentation/devicetree/bindings/pci/pci-keystone.txt

+1 −6
Original line number Diff line number Diff line
@@ -13,9 +13,7 @@ Required Properties:- 


compatibility: "ti,keystone-pcie"

reg:	index 1 is the base address and length of DW application registers.

	index 2 is the base address and length of PCI mode configuration

	register.

	index 3 is the base address and length of PCI device ID register.

	index 2 is the base address and length of PCI device ID register.



pcie_msi_intc : Interrupt controller device node for MSI IRQ chip

	interrupt-cells: should be set to 1
@@ -63,6 +61,3 @@ Designware DT Properties not applicable for Keystone PCI 


1. pcie_bus clock-names not used.  Instead, a phandle to phys is used.

Note for PCI driver usage

=========================

Driver requires pci=pcie_bus_perf in the bootargs for proper functioning.

drivers/pci/host/pci-imx6.c

+6 −5
Original line number Diff line number Diff line
@@ -257,11 +257,6 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) 
	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

	int ret;



	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);



	ret = clk_prepare_enable(imx6_pcie->pcie_phy);

	if (ret) {

		dev_err(pp->dev, "unable to enable pcie_phy clock\n");
@@ -283,6 +278,12 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) 
	/* allow the clocks to stabilize */

	usleep_range(200, 500);



	/* power up core phy and enable ref clock */

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);

	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);



	/* Some boards don't have PCIe reset GPIO. */

	if (gpio_is_valid(imx6_pcie->reset_gpio)) {

		gpio_set_value(imx6_pcie->reset_gpio, 0);

drivers/pci/host/pci-keystone.c

+52 −23
Original line number Diff line number Diff line
@@ -35,15 +35,56 @@ 
#define MAX_MSI_HOST_IRQS		8

#define MAX_LEGACY_HOST_IRQS		4



/* RC mode settings masks */

#define PCIE_RC_MODE		BIT(2)

#define PCIE_MODE_MASK		(BIT(1) | BIT(2))



/* DEV_STAT_CTRL */

#define PCIE_CAP_BASE		0x70



/* PCIE controller device IDs */

#define PCIE_RC_K2HK		0xb008

#define PCIE_RC_K2E		0xb009

#define PCIE_RC_K2L		0xb00a



#define to_keystone_pcie(x)	container_of(x, struct keystone_pcie, pp)



static void quirk_limit_mrrs(struct pci_dev *dev)

{

	struct pci_bus *bus = dev->bus;

	struct pci_dev *bridge = bus->self;

	static const struct pci_device_id rc_pci_devids[] = {

		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),

		 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },

		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),

		 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },

		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),

		 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },

		{ 0, },

	};



	if (pci_is_root_bus(bus))

		return;



	/* look for the host bridge */

	while (!pci_is_root_bus(bus)) {

		bridge = bus->self;

		bus = bus->parent;

	}



	if (bridge) {

		/*

		 * Keystone PCI controller has a h/w limitation of

		 * 256 bytes maximum read request size.  It can't handle

		 * anything higher than this.  So force this limit on

		 * all downstream devices.

		 */

		if (pci_match_id(rc_pci_devids, bridge)) {

			if (pcie_get_readrq(dev) > 256) {

				dev_info(&dev->dev, "limiting MRRS to 256\n");

				pcie_set_readrq(dev, 256);

			}

		}

	}

}

DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);



static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)

{

	struct pcie_port *pp = &ks_pcie->pp;
@@ -212,8 +253,8 @@ static int keystone_pcie_fault(unsigned long addr, unsigned int fsr, 


static void __init ks_pcie_host_init(struct pcie_port *pp)

{

	u32 vendor_device_id, val;

	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);

	u32 val;



	ks_pcie_establish_link(ks_pcie);

	ks_dw_pcie_setup_rc_app_regs(ks_pcie);
@@ -222,8 +263,7 @@ static void __init ks_pcie_host_init(struct pcie_port *pp) 
			pp->dbi_base + PCI_IO_BASE);



	/* update the Vendor ID */

	vendor_device_id = readl(ks_pcie->va_reg_pciid);

	writew((vendor_device_id >> 16), pp->dbi_base + PCI_DEVICE_ID);

	writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);



	/* update the DEV_STAT_CTRL to publish right mrrs */

	val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
@@ -310,7 +350,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) 
	void __iomem *reg_p;

	struct phy *phy;

	int ret = 0;

	u32 val;



	ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),

				GFP_KERNEL);
@@ -320,18 +359,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) 
	}

	pp = &ks_pcie->pp;



	/* index 2 is the devcfg register for RC mode settings */

	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);

	reg_p = devm_ioremap_resource(dev, res);

	if (IS_ERR(reg_p))

		return PTR_ERR(reg_p);



	/* enable RC mode in devcfg */

	val = readl(reg_p);

	val &= ~PCIE_MODE_MASK;

	val |= PCIE_RC_MODE;

	writel(val, reg_p);



	/* initialize SerDes Phy if present */

	phy = devm_phy_get(dev, "pcie-phy");

	if (!IS_ERR_OR_NULL(phy)) {
@@ -340,12 +367,14 @@ static int __init ks_pcie_probe(struct platform_device *pdev) 
			return ret;

	}



	/* index 3 is to read PCI DEVICE_ID */

	res = platform_get_resource(pdev, IORESOURCE_MEM, 3);

	/* index 2 is to read PCI DEVICE_ID */

	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);

	reg_p = devm_ioremap_resource(dev, res);

	if (IS_ERR(reg_p))

		return PTR_ERR(reg_p);

	ks_pcie->va_reg_pciid = reg_p;

	ks_pcie->device_id = readl(reg_p) >> 16;

	devm_iounmap(dev, reg_p);

	devm_release_mem_region(dev, res->start, resource_size(res));



	pp->dev = dev;

	platform_set_drvdata(pdev, ks_pcie);

drivers/pci/host/pci-keystone.h

+2 −2
Original line number Diff line number Diff line
@@ -19,8 +19,8 @@ 
struct keystone_pcie {

	struct	clk		*clk;

	struct	pcie_port	pp;

	void __iomem		*va_reg_pciid;



	/* PCI Device ID */

	u32			device_id;

	int			num_legacy_host_irqs;

	int			legacy_host_irqs[MAX_LEGACY_HOST_IRQS];

	struct			device_node *legacy_intc_np;