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Commit ed520c90 authored by Stephen Warren's avatar Stephen Warren
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ARM: tegra: document use of standard DMA DT bindings



Update all the Tegra DT bindings to require the standard dmas/dma-names
properties rather than non-standard nvidia,dma-request-selector property.

This is a DT-ABI-incompatible change. It is the second of two changes
required for me to consider the Tegra DT bindings as stable, the other
being the previous conversion to the common reset bindings.

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 07999587
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+5 −0
Original line number Diff line number Diff line
@@ -11,6 +11,10 @@ Required properties:
  See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
  - dma
- #dma-cells : Must be <1>. This dictates the length of DMA specifiers in
  client nodes' dmas properties. The specifier represents the DMA request
  select value for the peripheral. For more details, consult the Tegra TRM's
  documentation of the APB DMA channel control register REQ_SEL field.

Examples:

@@ -36,4 +40,5 @@ apbdma: dma@6000a000 {
	clocks = <&tegra_car 34>;
	resets = <&tegra_car 34>;
	reset-names = "dma";
	#dma-cells = <1>;
};
+7 −0
Original line number Diff line number Diff line
@@ -51,6 +51,11 @@ Required properties:
  See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
  - i2c
- dmas: Must contain an entry for each entry in clock-names.
  See ../dma/dma.txt for details.
- dma-names: Must include the following entries:
  - rx
  - tx

Example:

@@ -64,5 +69,7 @@ Example:
		clock-names = "div-clk", "fast-clk";
		resets = <&tegra_car 12>;
		reset-names = "i2c";
		dmas = <&apbdma 16>, <&apbdma 16>;
		dma-names = "rx", "tx";
		status = "disabled";
	};
+7 −3
Original line number Diff line number Diff line
@@ -4,14 +4,17 @@ Required properties:
- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
- reg: Should contain UART controller registers location and length.
- interrupts: Should contain UART controller interrupts.
- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
  request selector for this UART controller.
- clocks: Must contain one entry, for the module clock.
  See ../clocks/clock-bindings.txt for details.
- resets : Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
  - serial
- dmas : Must contain an entry for each entry in clock-names.
  See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
  - rx
  - tx

Optional properties:
- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
@@ -24,10 +27,11 @@ serial@70006000 {
	reg = <0x70006000 0x40>;
	reg-shift = <2>;
	interrupts = <0 36 0x04>;
	nvidia,dma-request-selector = <&apbdma 8>;
	nvidia,enable-modem-interrupt;
	clocks = <&tegra_car 6>;
	resets = <&tegra_car 6>;
	reset-names = "serial";
	dmas = <&apbdma 8>, <&apbdma 8>;
	dma-names = "rx", "tx";
	status = "disabled";
};
+9 −5
Original line number Diff line number Diff line
@@ -4,14 +4,17 @@ Required properties:
- compatible : "nvidia,tegra20-ac97"
- reg : Should contain AC97 controller registers location and length
- interrupts : Should contain AC97 interrupt
- clocks : Must contain one entry, for the module clock.
  See ../clocks/clock-bindings.txt for details.
- resets : Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
  - ac97
- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
  request selector for the AC97 controller
- dmas : Must contain an entry for each entry in clock-names.
  See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
  - rx
  - tx
- clocks : Must contain one entry, for the module clock.
  See ../clocks/clock-bindings.txt for details.
- nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
  of the GPIO used to reset the external AC97 codec
- nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number
@@ -23,10 +26,11 @@ ac97@70002000 {
	compatible = "nvidia,tegra20-ac97";
	reg = <0x70002000 0x200>;
	interrupts = <0 81 0x04>;
	nvidia,dma-request-selector = <&apbdma 12>;
	nvidia,codec-reset-gpio = <&gpio 170 0>;
	nvidia,codec-sync-gpio = <&gpio 120 0>;
	clocks = <&tegra_car 3>;
	resets = <&tegra_car 3>;
	reset-names = "ac97";
	dmas = <&apbdma 12>, <&apbdma 12>;
	dma-names = "rx", "tx";
};
+9 −5
Original line number Diff line number Diff line
@@ -4,14 +4,17 @@ Required properties:
- compatible : "nvidia,tegra20-i2s"
- reg : Should contain I2S registers location and length
- interrupts : Should contain I2S interrupt
- clocks : Must contain one entry, for the module clock.
  See ../clocks/clock-bindings.txt for details.
- resets : Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
  - i2s
- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
  request selector for this I2S controller
- dmas : Must contain an entry for each entry in clock-names.
  See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
  - rx
  - tx
- clocks : Must contain one entry, for the module clock.
  See ../clocks/clock-bindings.txt for details.

Example:

@@ -19,8 +22,9 @@ i2s@70002800 {
	compatible = "nvidia,tegra20-i2s";
	reg = <0x70002800 0x200>;
	interrupts = < 45 >;
	nvidia,dma-request-selector = < &apbdma 2 >;
	clocks = <&tegra_car 11>;
	resets = <&tegra_car 11>;
	reset-names = "i2s";
	dmas = <&apbdma 21>, <&apbdma 21>;
	dma-names = "rx", "tx";
};
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