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Commit ea584595 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'gpio-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio 

Pull GPIO changes from Linus Walleij:
 "This is the bulk of GPIO changes for the v3.18 development cycle:

   - Increase the default ARCH_NR_GPIO from 256 to 512.  This was done
     to avoid having a custom <asm/gpio.h> header for the x86
     architecture - GPIO is custom and complicated enough as it is
     already! We want to move to a radix to store the descriptors going
     forward, and finally get rid of this fixed array size altogether.

   - Endgame patching of the gpio_remove() semantics initiated by
     Abdoulaye Berthe.  It is not accepted by the system that the
     removal of a GPIO chip fails during eg reboot or shutdown, and
     therefore the return value has now painfully been refactored away.
     For special cases like GPIO expanders on a hot-pluggable bus like
     USB, we may later add some gpiochip_try_remove() call, but for the
     cases we have now, return values are moot.

   - Some incremental refactoring of the gpiolib core and ACPI GPIO
     library for more descriptor usage.

   - Refactor the chained IRQ handler set-up method to handle also
     threaded, nested interrupts and set up the parent IRQ correctly.
     Switch STMPE and TC3589x drivers to use this registration method.

   - Add a .irq_not_threaded flag to the struct gpio_chip, so that also
     GPIO expanders that block but are still not using threaded IRQ
     handlers.

   - New drivers for the ARM64 X-Gene SoC GPIO controller.

   - The syscon GPIO driver has been improved to handle the "DSP GPIO"
     found on the TI Keystone 2 SoC:s.

   - ADNP driver switched to use gpiolib irqchip helpers.

   - Refactor the DWAPB driver to support being instantiated from and
     MFD cell (platform device).

   - Incremental feature improvement in the Zynq, MCP23S08, DWAPB, OMAP,
     Xilinx and Crystalcove drivers.

   - Various minor fixes"

* tag 'gpio-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (52 commits)
  gpio: pch: Build context save/restore only for PM
  pinctrl: abx500: get rid of unused variable
  gpio: ks8695: fix 'else should follow close brace '}''
  gpio: stmpe: add verbose debug code
  gpio: stmpe: fix up interrupt enable logic
  gpio: staticize xway_stp_init()
  gpio: handle also nested irqchips in the chained handler set-up
  gpio: set parent irq on chained handlers
  gpiolib: irqchip: use irq_find_mapping while removing irqchip
  gpio: crystalcove: support virtual GPIO
  pinctrl: bcm281xx: make Kconfig dependency more strict
  gpio: kona: enable only on BCM_MOBILE or for compile testing
  gpio, bcm-kona, LLVMLinux: Remove use of __initconst
  gpio: Fix ngpio in gpio-xilinx driver
  gpio: dwapb: fix pointer to integer cast
  gpio: xgene: Remove unneeded #ifdef CONFIG_OF guard
  gpio: xgene: Remove unneeded forward declation for struct xgene_gpio
  gpio: xgene: Fix missing spin_lock_init()
  gpio: ks8695: fix switch case indentation
  gpiolib: add irq_not_threaded flag to gpio_chip
  ...
parents 782d59c5 a092e19b

Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt

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+39 −0
Original line number Diff line number Diff line 
Keystone 2 DSP GPIO controller bindings



HOST OS userland running on ARM can send interrupts to DSP cores using

the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.

This is one of the component used by the IPC mechanism used on Keystone SOCs.



For example TCI6638K2K SoC has 8 DSP GPIO controllers:

 - 8 for C66x CorePacx CPUs 0-7



Keystone 2 DSP GPIO controller has specific features:

- each GPIO can be configured only as output pin;

- setting GPIO value to 1 causes IRQ generation on target DSP core;

- reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still

  pending.



Required Properties:

- compatible: should be "ti,keystone-dsp-gpio"

- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to

  access device state control registers and the offset of device's specific

  registers within device state control registers range.

- gpio-controller: Marks the device node as a gpio controller.

- #gpio-cells: Should be 2.



Please refer to gpio.txt in this directory for details of the common GPIO

bindings used by client devices.



Example:

	dspgpio0: keystone_dsp_gpio@02620240 {

		compatible = "ti,keystone-dsp-gpio";

		ti,syscon-dev = <&devctrl 0x240>;

		gpio-controller;

		#gpio-cells = <2>;

	};



	dsp0: dsp0 {

		compatible = "linux,rproc-user";

		...

		kick-gpio = <&dspgpio0 27>;

	};

Documentation/devicetree/bindings/gpio/gpio-pca953x.txt

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* NXP PCA953x I2C GPIO multiplexer



Required properties:

 - compatible: Has to contain one of the following:

	nxp,pca9505

	nxp,pca9534

	nxp,pca9535

	nxp,pca9536

	nxp,pca9537

	nxp,pca9538

	nxp,pca9539

	nxp,pca9554

	nxp,pca9555

	nxp,pca9556

	nxp,pca9557

	nxp,pca9574

	nxp,pca9575

	nxp,pca9698

	maxim,max7310

	maxim,max7312

	maxim,max7313

	maxim,max7315

	ti,pca6107

	ti,tca6408

	ti,tca6416

	ti,tca6424

	exar,xra1202



Example:





	gpio@20 {

		compatible = "nxp,pca9505";

		reg = <0x20>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_pca9505>;

		interrupt-parent = <&gpio3>;

		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;

	};

Documentation/devicetree/bindings/gpio/gpio-xgene.txt

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+22 −0
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APM X-Gene SoC GPIO controller bindings



This is a gpio controller that is part of the flash controller.

This gpio controller controls a total of 48 gpios.



Required properties:

- compatible: "apm,xgene-gpio" for X-Gene GPIO controller

- reg: Physical base address and size of the controller's registers

- #gpio-cells: Should be two.

	- first cell is the pin number

	- second cell is used to specify the gpio polarity:

		0 = active high

		1 = active low

- gpio-controller: Marks the device node as a GPIO controller.



Example:

	gpio0: gpio0@1701c000 {

		compatible = "apm,xgene-gpio";

		reg = <0x0 0x1701c000 0x0 0x40>;

		gpio-controller;

		#gpio-cells = <2>;

	};

Documentation/devicetree/bindings/gpio/mrvl-gpio.txt

+14 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ Required properties: 
- gpio-controller : Marks the device node as a gpio controller.

- #gpio-cells : Should be one.  It is the pin number.



Example:

Example for a MMP platform:



	gpio: gpio@d4019000 {

		compatible = "marvell,mmp-gpio";
@@ -32,6 +32,19 @@ Example: 
		#interrupt-cells = <1>;

      };



Example for a PXA3xx platform:



	gpio: gpio@40e00000 {

		compatible = "intel,pxa3xx-gpio";

		reg = <0x40e00000 0x10000>;

		interrupt-names = "gpio0", "gpio1", "gpio_mux";

		interrupts = <8 9 10>;

		gpio-controller;

		#gpio-cells = <0x2>;

		interrupt-controller;

		#interrupt-cells = <0x2>;

	};



* Marvell Orion GPIO Controller



Required properties:

Documentation/gpio/driver.txt

+4 −2
Original line number Diff line number Diff line
@@ -124,7 +124,8 @@ symbol: 
* gpiochip_set_chained_irqchip(): sets up a chained irq handler for a

  gpio_chip from a parent IRQ and passes the struct gpio_chip* as handler

  data. (Notice handler data, since the irqchip data is likely used by the

  parent irqchip!) This is for the chained type of chip.

  parent irqchip!) This is for the chained type of chip. This is also used

  to set up a nested irqchip if NULL is passed as handler.



To use the helpers please keep the following in mind:
@@ -178,7 +179,8 @@ does not help since it pins the module to the kernel forever (it calls 
try_module_get()). A GPIO driver can use the following functions instead

to request and free descriptors without being pinned to the kernel forever.



	int gpiochip_request_own_desc(struct gpio_desc *desc, const char *label)

	struct gpio_desc *gpiochip_request_own_desc(struct gpio_desc *desc,

						    const char *label)



	void gpiochip_free_own_desc(struct gpio_desc *desc)