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Commit 782d59c5 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "The irq departement delivers:

   - a cleanup series to get rid of mindlessly copied code.

   - another bunch of new pointlessly different interrupt chip drivers.

     Adding homebrewn irq chips (and timers) to SoCs must provide a
     value add which is beyond the imagination of mere mortals.

   - the usual SoC irq controller updates, IOW my second cat herding
     project"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (44 commits)
  irqchip: gic-v3: Implement CPU PM notifier
  irqchip: gic-v3: Refactor gic_enable_redist to support both enabling and disabling
  irqchip: renesas-intc-irqpin: Add minimal runtime PM support
  irqchip: renesas-intc-irqpin: Add helper variable dev = &pdev->dev
  irqchip: atmel-aic5: Add sama5d4 support
  irqchip: atmel-aic5: The sama5d3 has 48 IRQs
  Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding
  irqchip: bcm7120-l2: Add Broadcom BCM7120-style Level 2 interrupt controller
  irqchip: renesas-irqc: Add binding docs for new R-Car Gen2 SoCs
  irqchip: renesas-irqc: Add DT binding documentation
  irqchip: renesas-intc-irqpin: Document SoC-specific bindings
  openrisc: Get rid of handle_IRQ
  arm64: Get rid of handle_IRQ
  ARM: omap2: irq: Convert to handle_domain_irq
  ARM: imx: tzic: Convert to handle_domain_irq
  ARM: imx: avic: Convert to handle_domain_irq
  irqchip: or1k-pic: Convert to handle_domain_irq
  irqchip: atmel-aic5: Convert to handle_domain_irq
  irqchip: atmel-aic: Convert to handle_domain_irq
  irqchip: gic-v3: Convert to handle_domain_irq
  ...
parents 47137c6b 2828c9cd

Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt

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Required properties:

- compatible: Should be "atmel,<chip>-aic"

  <chip> can be "at91rm9200" or "sama5d3"

  <chip> can be "at91rm9200", "sama5d3" or "sama5d4"

- interrupt-controller: Identifies the node as an interrupt controller.

- interrupt-parent: For single AIC system, it is an empty property.

- #interrupt-cells: The number of cells to define the interrupts. It should be 3.

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt

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Broadcom BCM7120-style Level 2 interrupt controller



This interrupt controller hardware is a second level interrupt controller that

is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based

platforms. It can be found on BCM7xxx products starting with BCM7120.



Such an interrupt controller has the following hardware design:



- outputs multiple interrupts signals towards its interrupt controller parent



- controls how some of the interrupts will be flowing, whether they will

  directly output an interrupt signal towards the interrupt controller parent,

  or if they will output an interrupt signal at this 2nd level interrupt

  controller, in particular for UARTs



- not all 32-bits within the interrupt controller actually map to an interrupt



The typical hardware layout for this controller is represented below:



2nd level interrupt line		Outputs for the parent controller (e.g: ARM GIC)



0 -----[ MUX ] ------------|==========> GIC interrupt 75

          \-----------\

                       |

1 -----[ MUX ] --------)---|==========> GIC interrupt 76

          \------------|

                       |

2 -----[ MUX ] --------)---|==========> GIC interrupt 77

          \------------|

                       |

3 ---------------------|

4 ---------------------|

5 ---------------------|

7 ---------------------|---|===========> GIC interrupt 66

9 ---------------------|

10 --------------------|

11 --------------------/



6 ------------------------\

                           |===========> GIC interrupt 64

8 ------------------------/



12 ........................ X

13 ........................ X 		(not connected)

..

31 ........................ X



Required properties:



- compatible: should be "brcm,bcm7120-l2-intc"

- reg: specifies the base physical address and size of the registers

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: specifies the number of cells needed to encode an interrupt

  source, should be 1.

- interrupt-parent: specifies the phandle to the parent interrupt controller

  this one is cascaded from

- interrupts: specifies the interrupt line(s) in the interrupt-parent controller

  node, valid values depend on the type of parent interrupt controller

- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts

  are wired to this 2nd level interrupt controller, and how they match their

  respective interrupt parents. Should match exactly the number of interrupts

  specified in the 'interrupts' property.



Optional properties:



- brcm,irq-can-wake: if present, this means the L2 controller can be used as a

  wakeup source for system suspend/resume.



- brcm,int-fwd-mask: if present, a 32-bits bit mask to configure for the

  interrupts which have a mux gate, typically UARTs. Setting these bits will

  make their respective interrupts outputs bypass this 2nd level interrupt

  controller completely, it completely transparent for the interrupt controller

  parent



Example:



irq0_intc: interrupt-controller@f0406800 {

	compatible = "brcm,bcm7120-l2-intc";

	interrupt-parent = <&intc>;

	#interrupt-cells = <1>;

	reg = <0xf0406800 0x8>;

	interrupt-controller;

	interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;

	brcm,int-map-mask = <0xeb8>, <0x140>;

	brcm,int-fwd-mask = <0x7>;

};

Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt

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Required properties:



- compatible: has to be "renesas,intc-irqpin"

- compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"

  as fallback.

  Examples with soctypes are:

    - "renesas,intc-irqpin-r8a7740" (R-Mobile A1)

    - "renesas,intc-irqpin-r8a7778" (R-Car M1A)

    - "renesas,intc-irqpin-r8a7779" (R-Car H1)

    - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)

- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in

  interrupts.txt in this directory

Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt

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DT bindings for the R-Mobile/R-Car interrupt controller



Required properties:



- compatible: has to be "renesas,irqc-<soctype>", "renesas,irqc" as fallback.

  Examples with soctypes are:

    - "renesas,irqc-r8a73a4" (R-Mobile AP6)

    - "renesas,irqc-r8a7790" (R-Car H2)

    - "renesas,irqc-r8a7791" (R-Car M2-W)

    - "renesas,irqc-r8a7792" (R-Car V2H)

    - "renesas,irqc-r8a7793" (R-Car M2-N)

    - "renesas,irqc-r8a7794" (R-Car E2)

- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in

  interrupts.txt in this directory



Optional properties:



- any properties, listed in interrupts.txt, and any standard resource allocation

  properties



Example:



	irqc0: interrupt-controller@e61c0000 {

		compatible = "renesas,irqc-r8a7790", "renesas,irqc";

		#interrupt-cells = <2>;

		interrupt-controller;

		reg = <0 0xe61c0000 0 0x200>;

		interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,

			     <0 1 IRQ_TYPE_LEVEL_HIGH>,

			     <0 2 IRQ_TYPE_LEVEL_HIGH>,

			     <0 3 IRQ_TYPE_LEVEL_HIGH>;

	};

Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt

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Keystone 2 IRQ controller IP



On Keystone SOCs, DSP cores can send interrupts to ARM

host using the IRQ controller IP. It provides 28 IRQ signals to ARM.

The IRQ handler running on HOST OS can identify DSP signal source by

analyzing SRCCx bits in IPCARx registers. This is one of the component

used by the IPC mechanism used on Keystone SOCs.



Required Properties:

- compatible: should be "ti,keystone-irq"

- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to

			access device control registers and the offset inside

			device control registers range.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode interrupt

					 source should be 1.

- interrupts: interrupt reference to primary interrupt controller



Please refer to interrupts.txt in this directory for details of the common

Interrupt Controllers bindings used by client devices.



Example:

	kirq0: keystone_irq0@026202a0 {

		compatible = "ti,keystone-irq";

		ti,syscon-dev = <&devctrl 0x2a0>;

		interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;

		interrupt-controller;

		#interrupt-cells = <1>;

	};



	dsp0: dsp0 {

		compatible = "linux,rproc-user";

		...

		interrupt-parent = <&kirq0>;

		interrupts = <10 2>;

	};