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Commit ea1f4e9d authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/host-tegra' into next 

* pci/host-tegra:
  PCI: tegra: Program PADS_REFCLK_CFG* registers with per-SoC values
  PCI: tegra: Program PADS_REFCLK_CFG* always, not just on legacy SoCs
  PCI: tegra: Stop setting pcibios_min_mem
  PCI: tegra: Use generic pci_remap_iospace() rather than ARM32-specific one
  PCI: tegra: Use lower-case hex consistently for register definitions

Conflicts:
	drivers/pci/host/pci-tegra.c

Drop stray pci_ioremap_io() per Thierry Reding <treding@nvidia.com>;
removal tested by Jon Hunter <jonathanh@nvidia.com>.
parents 79dd9934 f814430c

drivers/pci/host/pci-tegra.c

+25 −30
Original line number Diff line number Diff line
@@ -185,26 +185,26 @@ 


#define AFI_PEXBIAS_CTRL_0		0x168



#define RP_VEND_XP	0x00000F00

#define RP_VEND_XP	0x00000f00

#define  RP_VEND_XP_DL_UP	(1 << 30)



#define RP_PRIV_MISC	0x00000FE0

#define  RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)

#define  RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)

#define RP_PRIV_MISC	0x00000fe0

#define  RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0)

#define  RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0)



#define RP_LINK_CONTROL_STATUS			0x00000090

#define  RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE	0x20000000

#define  RP_LINK_CONTROL_STATUS_LINKSTAT_MASK	0x3fff0000



#define PADS_CTL_SEL		0x0000009C

#define PADS_CTL_SEL		0x0000009c



#define PADS_CTL		0x000000A0

#define PADS_CTL		0x000000a0

#define  PADS_CTL_IDDQ_1L	(1 << 0)

#define  PADS_CTL_TX_DATA_EN_1L	(1 << 6)

#define  PADS_CTL_RX_DATA_EN_1L	(1 << 10)



#define PADS_PLL_CTL_TEGRA20			0x000000B8

#define PADS_PLL_CTL_TEGRA30			0x000000B4

#define PADS_PLL_CTL_TEGRA20			0x000000b8

#define PADS_PLL_CTL_TEGRA30			0x000000b4

#define  PADS_PLL_CTL_RST_B4SM			(1 << 1)

#define  PADS_PLL_CTL_LOCKDET			(1 << 8)

#define  PADS_PLL_CTL_REFCLK_MASK		(0x3 << 16)
@@ -216,9 +216,9 @@ 
#define  PADS_PLL_CTL_TXCLKREF_DIV5		(1 << 20)

#define  PADS_PLL_CTL_TXCLKREF_BUF_EN		(1 << 22)



#define PADS_REFCLK_CFG0			0x000000C8

#define PADS_REFCLK_CFG1			0x000000CC

#define PADS_REFCLK_BIAS			0x000000D0

#define PADS_REFCLK_CFG0			0x000000c8

#define PADS_REFCLK_CFG1			0x000000cc

#define PADS_REFCLK_BIAS			0x000000d0



/*

 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
@@ -230,15 +230,6 @@ 
#define PADS_REFCLK_CFG_PREDI_SHIFT		8  /* 11:8 */

#define PADS_REFCLK_CFG_DRVI_SHIFT		12 /* 15:12 */



/* Default value provided by HW engineering is 0xfa5c */

#define PADS_REFCLK_CFG_VALUE \

	( \

		(0x17 << PADS_REFCLK_CFG_TERM_SHIFT)   | \

		(0    << PADS_REFCLK_CFG_E_TERM_SHIFT) | \

		(0xa  << PADS_REFCLK_CFG_PREDI_SHIFT)  | \

		(0xf  << PADS_REFCLK_CFG_DRVI_SHIFT)     \

	)



struct tegra_msi {

	struct msi_controller chip;

	DECLARE_BITMAP(used, INT_PCI_MSI_NR);
@@ -254,6 +245,8 @@ struct tegra_pcie_soc_data { 
	unsigned int msi_base_shift;

	u32 pads_pll_ctl;

	u32 tx_ref_sel;

	u32 pads_refclk_cfg0;

	u32 pads_refclk_cfg1;

	bool has_pex_clkreq_en;

	bool has_pex_bias_ctrl;

	bool has_intr_prsnt_sense;
@@ -628,8 +621,6 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) 
	if (err < 0)

		return err;



	pci_ioremap_io(pcie->pio.start, pcie->io.start);



	pci_add_resource_offset(&sys->resources, &pcie->pio, sys->io_offset);

	pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);

	pci_add_resource_offset(&sys->resources, &pcie->prefetch,
@@ -640,6 +631,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys) 
	if (err < 0)

		return err;



	pci_remap_iospace(&pcie->pio, pcie->io.start);

	return 1;

}
@@ -831,12 +823,6 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) 
	value |= PADS_PLL_CTL_RST_B4SM;

	pads_writel(pcie, value, soc->pads_pll_ctl);



	/* Configure the reference clock driver */

	value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);

	pads_writel(pcie, value, PADS_REFCLK_CFG0);

	if (soc->num_ports > 2)

		pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);



	/* wait for the PLL to lock */

	err = tegra_pcie_pll_wait(pcie, 500);

	if (err < 0) {
@@ -920,6 +906,7 @@ static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port) 


static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)

{

	const struct tegra_pcie_soc_data *soc = pcie->soc_data;

	struct tegra_pcie_port *port;

	int err;
@@ -945,6 +932,12 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie) 
		}

	}



	/* Configure the reference clock driver */

	pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);



	if (soc->num_ports > 2)

		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);



	return 0;

}
@@ -2055,6 +2048,7 @@ static const struct tegra_pcie_soc_data tegra20_pcie_data = { 
	.msi_base_shift = 0,

	.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,

	.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,

	.pads_refclk_cfg0 = 0xfa5cfa5c,

	.has_pex_clkreq_en = false,

	.has_pex_bias_ctrl = false,

	.has_intr_prsnt_sense = false,
@@ -2067,6 +2061,8 @@ static const struct tegra_pcie_soc_data tegra30_pcie_data = { 
	.msi_base_shift = 8,

	.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,

	.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,

	.pads_refclk_cfg0 = 0xfa5cfa5c,

	.pads_refclk_cfg1 = 0xfa5cfa5c,

	.has_pex_clkreq_en = true,

	.has_pex_bias_ctrl = true,

	.has_intr_prsnt_sense = true,
@@ -2079,6 +2075,7 @@ static const struct tegra_pcie_soc_data tegra124_pcie_data = { 
	.msi_base_shift = 8,

	.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,

	.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,

	.pads_refclk_cfg0 = 0x44ac44ac,

	.has_pex_clkreq_en = true,

	.has_pex_bias_ctrl = true,

	.has_intr_prsnt_sense = true,
@@ -2225,8 +2222,6 @@ static int tegra_pcie_probe(struct platform_device *pdev) 
	if (err < 0)

		return err;



	pcibios_min_mem = 0;



	err = tegra_pcie_get_resources(pcie);

	if (err < 0) {

		dev_err(&pdev->dev, "failed to request resources: %d\n", err);