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Commit 79dd9934 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branches 'pci/demodularize-hosts' and 'pci/host-request-windows' into next 

* pci/demodularize-hosts:
  PCI: xgene: Make explicitly non-modular
  PCI: thunder-pem: Make explicitly non-modular
  PCI: thunder-ecam: Make explicitly non-modular
  PCI: tegra: Make explicitly non-modular
  PCI: rcar-gen2: Make explicitly non-modular
  PCI: rcar: Make explicitly non-modular
  PCI: mvebu: Make explicitly non-modular
  PCI: layerscape: Make explicitly non-modular
  PCI: keystone: Make explicitly non-modular
  PCI: hisi: Make explicitly non-modular
  PCI: generic: Make explicitly non-modular
  PCI: designware-plat: Make it explicitly non-modular
  PCI: artpec6: Make explicitly non-modular
  PCI: armada8k: Make explicitly non-modular
  PCI: artpec: Add PCI_MSI_IRQ_DOMAIN dependency
  PCI: artpec: Add Axis ARTPEC-6 PCIe controller driver
  PCI: Add DT binding for Axis ARTPEC-6 PCIe controller
  PCI: generic: Select IRQ_DOMAIN

* pci/host-request-windows:
  PCI: versatile: Simplify host bridge window iteration
  PCI: versatile: Request host bridge window resources with core function
  PCI: tegra: Request host bridge window resources with core function
  PCI: tegra: Remove top-level resource from hierarchy
  PCI: rcar: Simplify host bridge window iteration
  PCI: rcar: Request host bridge window resources with core function
  PCI: rcar Gen2: Request host bridge window resources
  PCI: rcar: Drop gen2 dummy I/O port region
  ARM: Make PCI I/O space optional
  PCI: mvebu: Request host bridge window resources with core function
  PCI: generic: Simplify host bridge window iteration
  PCI: generic: Request host bridge window resources with core function
  PCI: altera: Simplify host bridge window iteration
  PCI: altera: Request host bridge window resources with core function
  PCI: xilinx-nwl: Use dev_printk() when possible
  PCI: xilinx-nwl: Request host bridge window resources
  PCI: xilinx-nwl: Free bridge resource list on failure
  PCI: xilinx: Request host bridge window resources
  PCI: xilinx: Free bridge resource list on failure
  PCI: xgene: Request host bridge window resources
  PCI: xgene: Free bridge resource list on failure
  PCI: iproc: Request host bridge window resources
  PCI: designware: Simplify host bridge window iteration
  PCI: designware: Request host bridge window resources
  PCI: designware: Free bridge resource list on failure
  PCI: Add devm_request_pci_bus_resources()
parents 3efc7023 50dcd290 da6163ad

Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt

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+46 −0
Original line number Diff line number Diff line 
* Axis ARTPEC-6 PCIe interface



This PCIe host controller is based on the Synopsys DesignWare PCIe IP

and thus inherits all the common properties defined in designware-pcie.txt.



Required properties:

- compatible: "axis,artpec6-pcie", "snps,dw-pcie"

- reg: base addresses and lengths of the PCIe controller (DBI),

	the phy controller, and configuration address space.

- reg-names: Must include the following entries:

	- "dbi"

	- "phy"

	- "config"

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

- interrupt-names: Must include the following entries:

	- "msi": The interrupt that is asserted when an MSI is received

- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,

	used to enable and control the Synopsys IP.



Example:



	pcie@f8050000 {

		compatible = "axis,artpec6-pcie", "snps,dw-pcie";

		reg = <0xf8050000 0x2000

		       0xf8040000 0x1000

		       0xc0000000 0x1000>;

		reg-names = "dbi", "phy", "config";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

			  /* downstream I/O */

		ranges = <0x81000000 0 0x00010000 0xc0010000 0 0x00010000

			  /* non-prefetchable memory */

			  0x82000000 0 0xc0020000 0xc0020000 0 0x1ffe0000>;

		num-lanes = <2>;

		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "msi";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0x7>;

		interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

		                <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

		                <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

		                <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;

		axis,syscon-pcie = <&syscon>;

	};

MAINTAINERS

+9 −0
Original line number Diff line number Diff line
@@ -8824,6 +8824,15 @@ S: Maintained 
F:	Documentation/devicetree/bindings/pci/xgene-pci-msi.txt

F:	drivers/pci/host/pci-xgene-msi.c



PCIE DRIVER FOR AXIS ARTPEC

M:	Niklas Cassel <niklas.cassel@axis.com>

M:	Jesper Nilsson <jesper.nilsson@axis.com>

L:	linux-arm-kernel@axis.com

L:	linux-pci@vger.kernel.org

S:	Maintained

F:	Documentation/devicetree/bindings/pci/axis,artpec*

F:	drivers/pci/host/*artpec*



PCIE DRIVER FOR HISILICON

M:	Zhou Wang <wangzhou1@hisilicon.com>

M:	Gabriele Paoloni <gabriele.paoloni@huawei.com>

arch/arm/include/asm/mach/pci.h

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ struct hw_pci { 
	struct msi_controller *msi_ctrl;

	struct pci_ops	*ops;

	int		nr_controllers;

	unsigned int	io_optional:1;

	void		**private_data;

	int		(*setup)(int nr, struct pci_sys_data *);

	struct pci_bus *(*scan)(int nr, struct pci_sys_data *);

arch/arm/kernel/bios32.c

+11 −2
Original line number Diff line number Diff line
@@ -410,7 +410,8 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 
	return irq;

}



static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)

static int pcibios_init_resource(int busnr, struct pci_sys_data *sys,

				 int io_optional)

{

	int ret;

	struct resource_entry *window;
@@ -420,6 +421,14 @@ static int pcibios_init_resources(int busnr, struct pci_sys_data *sys) 
			 &iomem_resource, sys->mem_offset);

	}



	/*

	 * If a platform says I/O port support is optional, we don't add

	 * the default I/O space.  The platform is responsible for adding

	 * any I/O space it needs.

	 */

	if (io_optional)

		return 0;



	resource_list_for_each_entry(window, &sys->resources)

		if (resource_type(window->res) == IORESOURCE_IO)

			return 0;
@@ -466,7 +475,7 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, 
		if (ret > 0) {

			struct pci_host_bridge *host_bridge;



			ret = pcibios_init_resources(nr, sys);

			ret = pcibios_init_resource(nr, sys, hw->io_optional);

			if (ret)  {

				kfree(sys);

				break;

drivers/pci/bus.c

+29 −1
Original line number Diff line number Diff line
@@ -91,6 +91,35 @@ void pci_bus_remove_resources(struct pci_bus *bus) 
	}

}



int devm_request_pci_bus_resources(struct device *dev,

				   struct list_head *resources)

{

	struct resource_entry *win;

	struct resource *parent, *res;

	int err;



	resource_list_for_each_entry(win, resources) {

		res = win->res;

		switch (resource_type(res)) {

		case IORESOURCE_IO:

			parent = &ioport_resource;

			break;

		case IORESOURCE_MEM:

			parent = &iomem_resource;

			break;

		default:

			continue;

		}



		err = devm_request_resource(dev, parent, res);

		if (err)

			return err;

	}



	return 0;

}

EXPORT_SYMBOL_GPL(devm_request_pci_bus_resources);



static struct pci_bus_region pci_32_bit = {0, 0xffffffffULL};

#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT

static struct pci_bus_region pci_64_bit = {0,
@@ -398,4 +427,3 @@ void pci_bus_put(struct pci_bus *bus) 
		put_device(&bus->dev);

}

EXPORT_SYMBOL(pci_bus_put);