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Commit e6d7f6dc authored by Sudeep Holla's avatar Sudeep Holla
Browse files

arm64: dts: Add support for Juno r2 board 



Juno r2 is identical to Juno r1 with Cortex A57 cores replaced by
Cortex A72 cores.

Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarLiviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent 36582c60

Documentation/devicetree/bindings/arm/arm-boards

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Original line number Original line Diff line number Diff line
@@ -180,6 +180,7 @@ described under the RS1 memory mapping. 
Required properties (in root node):

Required properties (in root node):

	compatible = "arm,juno";	/* For Juno r0 board */

	compatible = "arm,juno";	/* For Juno r0 board */

	compatible = "arm,juno-r1";	/* For Juno r1 board */

	compatible = "arm,juno-r1";	/* For Juno r1 board */

	compatible = "arm,juno-r2";	/* For Juno r2 board */





Required nodes:

Required nodes:

The description for the board must include:

The description for the board must include:

arch/arm64/boot/dts/arm/Makefile

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dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb foundation-v8-gicv3.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb foundation-v8-gicv3.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb

arch/arm64/boot/dts/arm/juno-r2.dts

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/*

 * ARM Ltd. Juno Platform

 *

 * Copyright (c) 2015 ARM Ltd.

 *

 * This file is licensed under a dual GPLv2 or BSD license.

 */



/dts-v1/;



#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	model = "ARM Juno development board (r2)";

	compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	aliases {

		serial0 = &soc_uart0;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&A72_0>;

				};

				core1 {

					cpu = <&A72_1>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&A53_0>;

				};

				core1 {

					cpu = <&A53_1>;

				};

				core2 {

					cpu = <&A53_2>;

				};

				core3 {

					cpu = <&A53_3>;

				};

			};

		};



		idle-states {

			entry-method = "arm,psci";



			CPU_SLEEP_0: cpu-sleep-0 {

				compatible = "arm,idle-state";

				arm,psci-suspend-param = <0x0010000>;

				local-timer-stop;

				entry-latency-us = <300>;

				exit-latency-us = <1200>;

				min-residency-us = <2000>;

			};



			CLUSTER_SLEEP_0: cluster-sleep-0 {

				compatible = "arm,idle-state";

				arm,psci-suspend-param = <0x1010000>;

				local-timer-stop;

				entry-latency-us = <300>;

				exit-latency-us = <1200>;

				min-residency-us = <2500>;

			};

		};



		A72_0: cpu@0 {

			compatible = "arm,cortex-a72","arm,armv8";

			reg = <0x0 0x0>;

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&A72_L2>;

			clocks = <&scpi_dvfs 0>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;

		};



		A72_1: cpu@1 {

			compatible = "arm,cortex-a72","arm,armv8";

			reg = <0x0 0x1>;

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&A72_L2>;

			clocks = <&scpi_dvfs 0>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;

		};



		A53_0: cpu@100 {

			compatible = "arm,cortex-a53","arm,armv8";

			reg = <0x0 0x100>;

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;

		};



		A53_1: cpu@101 {

			compatible = "arm,cortex-a53","arm,armv8";

			reg = <0x0 0x101>;

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;

		};



		A53_2: cpu@102 {

			compatible = "arm,cortex-a53","arm,armv8";

			reg = <0x0 0x102>;

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;

		};



		A53_3: cpu@103 {

			compatible = "arm,cortex-a53","arm,armv8";

			reg = <0x0 0x103>;

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;

		};



		A72_L2: l2-cache0 {

			compatible = "cache";

		};



		A53_L2: l2-cache1 {

			compatible = "cache";

		};

	};



	pmu_a72 {

		compatible = "arm,cortex-a72-pmu";

		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&A72_0>,

				     <&A72_1>;

	};



	pmu_a53 {

		compatible = "arm,cortex-a53-pmu";

		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&A53_0>,

				     <&A53_1>,

				     <&A53_2>,

				     <&A53_3>;

	};



	#include "juno-base.dtsi"

};



&memtimer {

	status = "okay";

};



&pcie_ctlr {

	status = "okay";

};