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Commit 36582c60 authored by Sudeep Holla's avatar Sudeep Holla
Browse files

arm64: dts: move juno pcie-controller to base file 



The PCIe controller is found on all Juno SoC version. However it's not
functional on R0 due to some hardware bug.

In preparation to add Juno R2 support, this patch moves the
pcie-controller defination to base DTS file. It's marked as disabled by
default and is enabled for Juno R1 explicitly.

Acked-by: default avatarLiviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent 6ba29e91

arch/arm64/boot/dts/arm/juno-base.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -75,6 +75,28 @@ 
		};

	};



	pcie_ctlr: pcie-controller@40000000 {

		compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";

		device_type = "pci";

		reg = <0 0x40000000 0 0x10000000>;	/* ECAM config space */

		bus-range = <0 255>;

		linux,pci-domain = <0>;

		#address-cells = <3>;

		#size-cells = <2>;

		dma-coherent;

		ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,

			 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,

			 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,

				<0 0 0 2 &gic 0 0 0 137 4>,

				<0 0 0 3 &gic 0 0 0 138 4>,

				<0 0 0 4 &gic 0 0 0 139 4>;

		msi-parent = <&v2m_0>;

		status = "disabled";

	};



	scpi {

		compatible = "arm,scpi";

		mboxes = <&mailbox 1>;

arch/arm64/boot/dts/arm/juno-r1.dts

+4 −21
Original line number Diff line number Diff line
@@ -172,29 +172,12 @@ 
	};



	#include "juno-base.dtsi"



	pcie-controller@40000000 {

		compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";

		device_type = "pci";

		reg = <0 0x40000000 0 0x10000000>;	/* ECAM config space */

		bus-range = <0 255>;

		linux,pci-domain = <0>;

		#address-cells = <3>;

		#size-cells = <2>;

		dma-coherent;

		ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,

			 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,

			 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,

				<0 0 0 2 &gic 0 0 0 137 4>,

				<0 0 0 3 &gic 0 0 0 138 4>,

				<0 0 0 4 &gic 0 0 0 139 4>;

		msi-parent = <&v2m_0>;

	};

};



&memtimer {

	status = "okay";

};



&pcie_ctlr {

	status = "okay";

};