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Commit e6b6dc7f authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branch 'gic' into HEAD 

* arm64-prep-gic:
  irqchip: gic: Perform the gic_secondary_init() call via CPU notifier
  irqchip: gic: Call handle_bad_irq() directly
  arm: Move chained_irq_(enter|exit) to a generic file
  arm: Move the set_handle_irq and handle_arch_irq declarations to asm/irq.h
parents 16c85a1f c0114709

arch/arm/include/asm/irq.h

+5 −0
Original line number Diff line number Diff line
@@ -30,6 +30,11 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *); 
void handle_IRQ(unsigned int, struct pt_regs *);

void init_IRQ(void);



#ifdef CONFIG_MULTI_IRQ_HANDLER

extern void (*handle_arch_irq)(struct pt_regs *);

extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));

#endif



#endif



#endif

arch/arm/include/asm/mach/irq.h

+0 −36
Original line number Diff line number Diff line
@@ -20,11 +20,6 @@ struct seq_file; 
extern void init_FIQ(int);

extern int show_fiq_list(struct seq_file *, int);



#ifdef CONFIG_MULTI_IRQ_HANDLER

extern void (*handle_arch_irq)(struct pt_regs *);

extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));

#endif



/*

 * This is for easy migration, but should be changed in the source

 */
@@ -35,35 +30,4 @@ do { \ 
	raw_spin_unlock(&desc->lock);			\

} while(0)



#ifndef __ASSEMBLY__

/*

 * Entry/exit functions for chained handlers where the primary IRQ chip

 * may implement either fasteoi or level-trigger flow control.

 */

static inline void chained_irq_enter(struct irq_chip *chip,

				     struct irq_desc *desc)

{

	/* FastEOI controllers require no action on entry. */

	if (chip->irq_eoi)

		return;



	if (chip->irq_mask_ack) {

		chip->irq_mask_ack(&desc->irq_data);

	} else {

		chip->irq_mask(&desc->irq_data);

		if (chip->irq_ack)

			chip->irq_ack(&desc->irq_data);

	}

}



static inline void chained_irq_exit(struct irq_chip *chip,

				    struct irq_desc *desc)

{

	if (chip->irq_eoi)

		chip->irq_eoi(&desc->irq_data);

	else

		chip->irq_unmask(&desc->irq_data);

}

#endif



#endif

arch/arm/mach-at91/gpio.c

+1 −2
Original line number Diff line number Diff line
@@ -22,10 +22,9 @@ 
#include <linux/module.h>

#include <linux/io.h>

#include <linux/irqdomain.h>

#include <linux/irqchip/chained_irq.h>

#include <linux/of_address.h>



#include <asm/mach/irq.h>



#include <mach/hardware.h>

#include <mach/at91_pio.h>

arch/arm/mach-exynos/common.c

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include <linux/irqchip.h>

#include <linux/of_address.h>

#include <linux/irqchip/arm-gic.h>

#include <linux/irqchip/chained_irq.h>



#include <asm/proc-fns.h>

#include <asm/exception.h>

arch/arm/mach-exynos/platsmp.c

+0 −8
Original line number Diff line number Diff line
@@ -20,7 +20,6 @@ 
#include <linux/jiffies.h>

#include <linux/smp.h>

#include <linux/io.h>

#include <linux/irqchip/arm-gic.h>



#include <asm/cacheflush.h>

#include <asm/smp_plat.h>
@@ -75,13 +74,6 @@ static DEFINE_SPINLOCK(boot_lock); 


static void __cpuinit exynos_secondary_init(unsigned int cpu)

{

	/*

	 * if any interrupts are already enabled for the primary

	 * core (e.g. timer irq), then they will not have been enabled

	 * for us: do so

	 */

	gic_secondary_init(0);



	/*

	 * let the primary processor know we're out of the

	 * pen, then head off into the C entry point