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Commit c0114709 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

irqchip: gic: Perform the gic_secondary_init() call via CPU notifier 



All the calls to gic_secondary_init() pass 0 as the first argument.
Since this function is called on each CPU when starting, it can be done
in a platform-independent way via a CPU notifier registered by the GIC
code.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Acked-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: default avatarRob Herring <rob.herring@calxeda.com>
Acked-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Tested-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Acked-by: default avatarSrinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Tested-by: default avatarDinh Nguyen <dinguyen@altera.com>
Acked-by: default avatarNicolas Pitre <nico@linaro.org>
Tested-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Barry Song <baohua.song@csr.com>
parent aec00956

arch/arm/mach-exynos/platsmp.c

+0 −8
Original line number Original line Diff line number Diff line
@@ -20,7 +20,6 @@ 
#include <linux/jiffies.h>

#include <linux/jiffies.h>

#include <linux/smp.h>

#include <linux/smp.h>

#include <linux/io.h>

#include <linux/io.h>

#include <linux/irqchip/arm-gic.h>





#include <asm/cacheflush.h>

#include <asm/cacheflush.h>

#include <asm/smp_plat.h>

#include <asm/smp_plat.h>
@@ -75,13 +74,6 @@ static DEFINE_SPINLOCK(boot_lock); 




static void __cpuinit exynos_secondary_init(unsigned int cpu)

static void __cpuinit exynos_secondary_init(unsigned int cpu)

{

{

	/*

	 * if any interrupts are already enabled for the primary

	 * core (e.g. timer irq), then they will not have been enabled

	 * for us: do so

	 */

	gic_secondary_init(0);



	/*

	/*

	 * let the primary processor know we're out of the

	 * let the primary processor know we're out of the

	 * pen, then head off into the C entry point

	 * pen, then head off into the C entry point

arch/arm/mach-highbank/platsmp.c

+0 −7
Original line number Original line Diff line number Diff line
@@ -17,7 +17,6 @@ 
#include <linux/init.h>

#include <linux/init.h>

#include <linux/smp.h>

#include <linux/smp.h>

#include <linux/io.h>

#include <linux/io.h>

#include <linux/irqchip/arm-gic.h>





#include <asm/smp_scu.h>

#include <asm/smp_scu.h>
@@ -25,11 +24,6 @@ 




extern void secondary_startup(void);

extern void secondary_startup(void);





static void __cpuinit highbank_secondary_init(unsigned int cpu)

{

	gic_secondary_init(0);

}



static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)

static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)

{

{

	highbank_set_cpu_jump(cpu, secondary_startup);

	highbank_set_cpu_jump(cpu, secondary_startup);
@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus) 
struct smp_operations highbank_smp_ops __initdata = {

struct smp_operations highbank_smp_ops __initdata = {

	.smp_init_cpus		= highbank_smp_init_cpus,

	.smp_init_cpus		= highbank_smp_init_cpus,

	.smp_prepare_cpus	= highbank_smp_prepare_cpus,

	.smp_prepare_cpus	= highbank_smp_prepare_cpus,

	.smp_secondary_init	= highbank_secondary_init,

	.smp_boot_secondary	= highbank_boot_secondary,

	.smp_boot_secondary	= highbank_boot_secondary,

#ifdef CONFIG_HOTPLUG_CPU

#ifdef CONFIG_HOTPLUG_CPU

	.cpu_die		= highbank_cpu_die,

	.cpu_die		= highbank_cpu_die,

arch/arm/mach-imx/platsmp.c

+0 −12
Original line number Original line Diff line number Diff line
@@ -12,7 +12,6 @@ 




#include <linux/init.h>

#include <linux/init.h>

#include <linux/smp.h>

#include <linux/smp.h>

#include <linux/irqchip/arm-gic.h>

#include <asm/page.h>

#include <asm/page.h>

#include <asm/smp_scu.h>

#include <asm/smp_scu.h>

#include <asm/mach/map.h>

#include <asm/mach/map.h>
@@ -52,16 +51,6 @@ void imx_scu_standby_enable(void) 
	writel_relaxed(val, scu_base);

	writel_relaxed(val, scu_base);

}

}





static void __cpuinit imx_secondary_init(unsigned int cpu)

{

	/*

	 * if any interrupts are already enabled for the primary

	 * core (e.g. timer irq), then they will not have been enabled

	 * for us: do so

	 */

	gic_secondary_init(0);

}



static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)

static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)

{

{

	imx_set_cpu_jump(cpu, v7_secondary_startup);

	imx_set_cpu_jump(cpu, v7_secondary_startup);
@@ -96,7 +85,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus) 
struct smp_operations  imx_smp_ops __initdata = {

struct smp_operations  imx_smp_ops __initdata = {

	.smp_init_cpus		= imx_smp_init_cpus,

	.smp_init_cpus		= imx_smp_init_cpus,

	.smp_prepare_cpus	= imx_smp_prepare_cpus,

	.smp_prepare_cpus	= imx_smp_prepare_cpus,

	.smp_secondary_init	= imx_secondary_init,

	.smp_boot_secondary	= imx_boot_secondary,

	.smp_boot_secondary	= imx_boot_secondary,

#ifdef CONFIG_HOTPLUG_CPU

#ifdef CONFIG_HOTPLUG_CPU

	.cpu_die		= imx_cpu_die,

	.cpu_die		= imx_cpu_die,

arch/arm/mach-msm/platsmp.c

+0 −8
Original line number Original line Diff line number Diff line
@@ -15,7 +15,6 @@ 
#include <linux/jiffies.h>

#include <linux/jiffies.h>

#include <linux/smp.h>

#include <linux/smp.h>

#include <linux/io.h>

#include <linux/io.h>

#include <linux/irqchip/arm-gic.h>





#include <asm/cacheflush.h>

#include <asm/cacheflush.h>

#include <asm/cputype.h>

#include <asm/cputype.h>
@@ -41,13 +40,6 @@ static inline int get_core_count(void) 




static void __cpuinit msm_secondary_init(unsigned int cpu)

static void __cpuinit msm_secondary_init(unsigned int cpu)

{

{

	/*

	 * if any interrupts are already enabled for the primary

	 * core (e.g. timer irq), then they will not have been enabled

	 * for us: do so

	 */

	gic_secondary_init(0);



	/*

	/*

	 * let the primary processor know we're out of the

	 * let the primary processor know we're out of the

	 * pen, then head off into the C entry point

	 * pen, then head off into the C entry point

arch/arm/mach-omap2/omap-smp.c

+0 −7
Original line number Original line Diff line number Diff line
@@ -66,13 +66,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu) 
		omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,

		omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,

							4, 0, 0, 0, 0, 0);

							4, 0, 0, 0, 0, 0);





	/*

	 * If any interrupts are already enabled for the primary

	 * core (e.g. timer irq), then they will not have been enabled

	 * for us: do so

	 */

	gic_secondary_init(0);



	/*

	/*

	 * Synchronise with the boot thread.

	 * Synchronise with the boot thread.

	 */

	 */