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Commit e5cc6aa4 authored by Marcin Tomczak's avatar Marcin Tomczak Committed by James Bottomley
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[SCSI] isci: enable clock gating



Enabling clock gating for power savings on entry to controller ready
state. Disable SCU clock gating for power savings on exit from the
controller ready state.

The gating is fully automated by silicon after setting the mode.

Signed-off-by: default avatarMarcin Tomczak <marcin.tomczak@intel.com>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent e3d338a5
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