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Commit e4e0c058 authored by Eugeni Dodonov's avatar Eugeni Dodonov Committed by Jesse Barnes
Browse files

drm/i915: gen7: Implement an L3 caching workaround. 

This adds two cache-related workarounds for Ivy Bridge which can lead to
3D ring hangs and corruptions.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44610


Tested-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarKenneth Graunke <kenneth@whitecape.org>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
parent eae66b50

drivers/gpu/drm/i915/i915_reg.h

+7 −0
Original line number Diff line number Diff line
@@ -3028,6 +3028,13 @@ 
#define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)

#define  DISP_FBC_WM_DIS		(1<<15)



/* GEN7 chicken */

#define GEN7_L3CNTLREG1				0xB01C

#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C



#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030

#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000



/* PCH */



/* south display engine interrupt */

drivers/gpu/drm/i915/intel_display.c

+6 −0
Original line number Diff line number Diff line
@@ -8472,6 +8472,12 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |

		   CHICKEN3_DGMG_DONE_FIX_DISABLE);



	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */

	I915_WRITE(GEN7_L3CNTLREG1,

			GEN7_WA_FOR_GEN7_L3_CONTROL);

	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,

			GEN7_WA_L3_CHICKEN_MODE);



	for_each_pipe(pipe) {

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |