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Commit eae66b50 authored by Eugeni Dodonov's avatar Eugeni Dodonov Committed by Jesse Barnes
Browse files

drm/i915: gen7: implement rczunit workaround 

This is yet another workaround related to clock gating which we need on
Ivy Bridge.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44610


Tested-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarKenneth Graunke <kenneth@whitecape.org>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
parent 8597559a

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -3618,6 +3618,7 @@ 
#define    GT_FIFO_NUM_RESERVED_ENTRIES		20



#define GEN6_UCGCTL2				0x9404

# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)

# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)

# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)

drivers/gpu/drm/i915/intel_display.c

+5 −0
Original line number Diff line number Diff line
@@ -8461,6 +8461,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);



	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.

	 * This implements the WaDisableRCZUnitClockGating workaround.

	 */

	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);



	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);



	I915_WRITE(IVB_CHICKEN3,