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Commit e39bf98a authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915/bdw: get the correct LCPLL frequency on Broadwell 



v2: Rebased onto Paulo's MHz->kHz change.

v3: Rebased on top of the Haswell pc8+ adjustements.

v4: Use the exact 337.5MHz clock, should have been done as part of v2.

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 756f85cf

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -5315,6 +5315,9 @@ 
#define  LCPLL_PLL_LOCK			(1<<30)

#define  LCPLL_CLK_FREQ_MASK		(3<<26)

#define  LCPLL_CLK_FREQ_450		(0<<26)

#define  LCPLL_CLK_FREQ_54O_BDW		(1<<26)

#define  LCPLL_CLK_FREQ_337_5_BDW	(2<<26)

#define  LCPLL_CLK_FREQ_675_BDW		(3<<26)

#define  LCPLL_CD_CLOCK_DISABLE		(1<<25)

#define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)

#define  LCPLL_POWER_DOWN_ALLOW		(1<<22)

drivers/gpu/drm/i915/intel_ddi.c

+18 −7
Original line number Diff line number Diff line
@@ -1158,18 +1158,29 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder) 


int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)

{

	struct drm_device *dev = dev_priv->dev;

	uint32_t lcpll = I915_READ(LCPLL_CTL);

	uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;



	if (lcpll & LCPLL_CD_SOURCE_FCLK)

	if (lcpll & LCPLL_CD_SOURCE_FCLK) {

		return 800000;

	else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)

	} else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) {

		return 450000;

	else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_450)

	} else if (freq == LCPLL_CLK_FREQ_450) {

		return 450000;

	else if (IS_ULT(dev_priv->dev))

	} else if (IS_HASWELL(dev)) {

		if (IS_ULT(dev))

			return 337500;

		else

			return 540000;

	} else {

		if (freq == LCPLL_CLK_FREQ_54O_BDW)

			return 540000;

		else if (freq == LCPLL_CLK_FREQ_337_5_BDW)

			return 337500;

		else

			return 675000;

	}

}



void intel_ddi_pll_init(struct drm_device *dev)