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Commit 756f85cf authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915/bdw: Broadwell has PIPEMISC 



And it inherits some bits from the previous TRANS_CONF (aka PIPE_CONF
on previous gens).

v2: Rebase on to of the pipe config bpp handling rework.

v3: Rebased on top of the pipe_config->dither refactoring.

v4: Drop the read-modify-write cycle for PIPEMISC, similarly to how we
now also build up PIPECONF completely ourselves - keeping around
random stuff set by the BIOS just isn't a good idea. I've checked BDW
BSpec and we already set all relevant bits.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent c7670b10

drivers/gpu/drm/i915/i915_reg.h

+12 −0
Original line number Diff line number Diff line
@@ -3237,6 +3237,18 @@ 
#define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)

#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)



#define _PIPE_MISC_A			0x70030

#define _PIPE_MISC_B			0x71030

#define   PIPEMISC_DITHER_BPC_MASK	(7<<5)

#define   PIPEMISC_DITHER_8_BPC		(0<<5)

#define   PIPEMISC_DITHER_10_BPC	(1<<5)

#define   PIPEMISC_DITHER_6_BPC		(2<<5)

#define   PIPEMISC_DITHER_12_BPC	(3<<5)

#define   PIPEMISC_DITHER_ENABLE	(1<<4)

#define   PIPEMISC_DITHER_TYPE_MASK	(3<<2)

#define   PIPEMISC_DITHER_TYPE_SP	(0<<2)

#define PIPEMISC(pipe) _PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)



#define VLV_DPFLIPSTAT				(VLV_DISPLAY_BASE + 0x70028)

#define   PIPEB_LINE_COMPARE_INT_EN		(1<<29)

#define   PIPEB_HLINE_INT_EN			(1<<28)

drivers/gpu/drm/i915/intel_display.c

+31 −2
Original line number Diff line number Diff line
@@ -5818,14 +5818,16 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc) 


static void haswell_set_pipeconf(struct drm_crtc *crtc)

{

	struct drm_i915_private *dev_priv = crtc->dev->dev_private;

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	enum pipe pipe = intel_crtc->pipe;

	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;

	uint32_t val;



	val = 0;



	if (intel_crtc->config.dither)

	if (IS_HASWELL(dev) && intel_crtc->config.dither)

		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);



	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
@@ -5838,6 +5840,33 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc) 


	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);

	POSTING_READ(GAMMA_MODE(intel_crtc->pipe));



	if (IS_BROADWELL(dev)) {

		val = 0;



		switch (intel_crtc->config.pipe_bpp) {

		case 18:

			val |= PIPEMISC_DITHER_6_BPC;

			break;

		case 24:

			val |= PIPEMISC_DITHER_8_BPC;

			break;

		case 30:

			val |= PIPEMISC_DITHER_10_BPC;

			break;

		case 36:

			val |= PIPEMISC_DITHER_12_BPC;

			break;

		default:

			/* Case prevented by pipe_config_set_bpp. */

			BUG();

		}



		if (intel_crtc->config.dither)

			val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;



		I915_WRITE(PIPEMISC(pipe), val);

	}

}



static bool ironlake_compute_clocks(struct drm_crtc *crtc,