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Commit dff8a207 authored by Keerthy's avatar Keerthy Committed by Tero Kristo
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ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk clock 



cpsw needs the clock to be running at 50MHz in kernel. Hence setting
the default rate.

Signed-off-by: default avatarKeerthy <j-keerthy@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent 93c03a2c

arch/arm/boot/dts/am4372.dtsi

+5 −2
Original line number Diff line number Diff line
@@ -527,8 +527,11 @@ 
			#address-cells = <1>;

			#size-cells = <1>;

			ti,hwmods = "cpgmac0";

			clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;

			clock-names = "fck", "cpts";

			clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,

				 <&dpll_clksel_mac_clk>;

			clock-names = "fck", "cpts", "50mclk";

			assigned-clocks = <&dpll_clksel_mac_clk>;

			assigned-clock-rates = <50000000>;

			status = "disabled";

			cpdma_channels = <8>;

			ale_entries = <1024>;