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Commit 93c03a2c authored by Keerthy's avatar Keerthy Committed by Tero Kristo
Browse files

ARM: dts: AM437X: add dpll_clksel_mac_clk node 



The patch adds the missing dpll_clksel_mac_clk clock node.

Signed-off-by: default avatarKeerthy <j-keerthy@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent bc0195aa

arch/arm/boot/dts/am43xx-clocks.dtsi

+9 −0
Original line number Original line Diff line number Diff line
@@ -486,6 +486,15 @@ 
		reg = <0x4238>;

		reg = <0x4238>;

	};

	};





	dpll_clksel_mac_clk: dpll_clksel_mac_clk {

		#clock-cells = <0>;

		compatible = "ti,divider-clock";

		clocks = <&dpll_core_m5_ck>;

		reg = <0x4234>;

		ti,bit-shift = <2>;

		ti,dividers = <2>, <5>;

	};



	clk_32k_mosc_ck: clk_32k_mosc_ck {

	clk_32k_mosc_ck: clk_32k_mosc_ck {

		#clock-cells = <0>;

		#clock-cells = <0>;

		compatible = "fixed-clock";

		compatible = "fixed-clock";

drivers/clk/ti/clk-43xx.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -71,6 +71,7 @@ static struct ti_dt_clk am43xx_clks[] = { 
	DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),

	DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),

	DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),

	DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),

	DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),

	DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),

	DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"),

	DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),

	DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),

	DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),

	DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),

	DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),

	DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),