Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit dfcef252 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: correctly set the DDI_FUNC_CTL bpc field 



Correctly erase the values previously set and also check for 6bpc and
10bpc.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f63eb7c4

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -4308,6 +4308,7 @@ 
#define  PIPE_DDI_MODE_SELECT_DP_SST	(2<<24)

#define  PIPE_DDI_MODE_SELECT_DP_MST	(3<<24)

#define  PIPE_DDI_MODE_SELECT_FDI		(4<<24)

#define  PIPE_DDI_BPC_MASK			(7<<20)

#define  PIPE_DDI_BPC_8					(0<<20)

#define  PIPE_DDI_BPC_10				(1<<20)

#define  PIPE_DDI_BPC_6					(2<<20)

drivers/gpu/drm/i915/intel_ddi.c

+20 −6
Original line number Diff line number Diff line
@@ -725,14 +725,28 @@ void intel_ddi_mode_set(struct drm_encoder *encoder, 
	/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */

	temp = I915_READ(DDI_FUNC_CTL(pipe));

	temp &= ~PIPE_DDI_PORT_MASK;

	temp &= ~PIPE_DDI_BPC_12;

	temp &= ~PIPE_DDI_BPC_MASK;

	temp &= ~PIPE_DDI_MODE_SELECT_MASK;

	temp &= ~(PIPE_DDI_PVSYNC | PIPE_DDI_PHSYNC);

	temp |= PIPE_DDI_SELECT_PORT(port) |

			((intel_crtc->bpp > 24) ?

				PIPE_DDI_BPC_12 :

				PIPE_DDI_BPC_8) |

			PIPE_DDI_FUNC_ENABLE;

	temp |= PIPE_DDI_FUNC_ENABLE | PIPE_DDI_SELECT_PORT(port);



	switch (intel_crtc->bpp) {

	case 18:

		temp |= PIPE_DDI_BPC_6;

		break;

	case 24:

		temp |= PIPE_DDI_BPC_8;

		break;

	case 30:

		temp |= PIPE_DDI_BPC_10;

		break;

	case 36:

		temp |= PIPE_DDI_BPC_12;

		break;

	default:

		WARN(1, "%d bpp unsupported by pipe DDI function\n",

		     intel_crtc->bpp);

	}



	if (intel_hdmi->has_hdmi_sink)

		temp |= PIPE_DDI_MODE_SELECT_HDMI;