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Commit cc0cb67a authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branches 'pci/aer' and 'pci/virtualization' into next 

* pci/aer:
  PCI/AER: Rename PCI_ERR_UNC_TRAIN to PCI_ERR_UNC_UND
  PCI/AER: Add additional PCIe AER error strings
  trace, RAS: Add additional PCIe AER error strings
  trace, RAS: Replace bare numbers with #defines for PCIe AER error strings

* pci/virtualization:
  PCI: Add ACS quirk for Intel 10G NICs
parents 1104528b 846fc709 100ebb2c

drivers/pci/pcie/aer/aerdrv_errprint.c

+9 −2
Original line number Diff line number Diff line
@@ -89,15 +89,17 @@ static const char *aer_correctable_error_string[] = { 
	NULL,

	"Replay Timer Timeout",		/* Bit Position 12	*/

	"Advisory Non-Fatal",		/* Bit Position 13	*/

	"Corrected Internal Error",	/* Bit Position 14	*/

	"Header Log Overflow",		/* Bit Position 15	*/

};



static const char *aer_uncorrectable_error_string[] = {

	NULL,

	"Undefined",			/* Bit Position 0	*/

	NULL,

	NULL,

	NULL,

	"Data Link Protocol",		/* Bit Position 4	*/

	NULL,

	"Surprise Down Error",		/* Bit Position 5	*/

	NULL,

	NULL,

	NULL,
@@ -113,6 +115,11 @@ static const char *aer_uncorrectable_error_string[] = { 
	"Malformed TLP",		/* Bit Position 18	*/

	"ECRC",				/* Bit Position 19	*/

	"Unsupported Request",		/* Bit Position 20	*/

	"ACS Violation",		/* Bit Position 21	*/

	"Uncorrectable Internal Error",	/* Bit Position 22	*/

	"MC Blocked TLP",		/* Bit Position 23	*/

	"AtomicOp Egress Blocked",	/* Bit Position 24	*/

	"TLP Prefix Blocked Error",	/* Bit Position 25	*/

};



static const char *aer_agent_string[] = {

drivers/pci/quirks.c

+28 −6
Original line number Diff line number Diff line
@@ -3635,14 +3635,16 @@ static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 
	return acs_flags & ~flags ? 0 : 1;

}



static int pci_quirk_solarflare_acs(struct pci_dev *dev, u16 acs_flags)

static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)

{

	/*

	 * SV, TB, and UF are not relevant to multifunction endpoints.

	 *

	 * Solarflare indicates that peer-to-peer between functions is not

	 * possible, therefore RR, CR, and DT are not implemented.  Mask

	 * these out as if they were clear in the ACS capabilities register.

	 * Multifunction devices are only required to implement RR, CR, and DT

	 * in their ACS capability if they support peer-to-peer transactions.

	 * Devices matching this quirk have been verified by the vendor to not

	 * perform peer-to-peer with other functions, allowing us to mask out

	 * these bits as if they were unimplemented in the ACS capability.

	 */

	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |

		       PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
@@ -3661,8 +3663,28 @@ static const struct pci_dev_acs_enabled { 
	{ PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },

	{ PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },

	{ PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },

	{ PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_solarflare_acs },

	{ PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_solarflare_acs },

	{ PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },

	{ 0 }

};

drivers/vfio/pci/vfio_pci_config.c

+1 −1
Original line number Diff line number Diff line
@@ -727,7 +727,7 @@ static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm) 
	p_setd(perm, 0, ALL_VIRT, NO_WRITE);



	/* Writable bits mask */

	mask =	PCI_ERR_UNC_TRAIN |		/* Training */

	mask =	PCI_ERR_UNC_UND |		/* Undefined */

		PCI_ERR_UNC_DLP |		/* Data Link Protocol */

		PCI_ERR_UNC_SURPDN |		/* Surprise Down */

		PCI_ERR_UNC_POISON_TLP |	/* Poisoned TLP */

include/ras/ras_event.h

+29 −19
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <linux/tracepoint.h>

#include <linux/edac.h>

#include <linux/ktime.h>

#include <linux/pci.h>

#include <linux/aer.h>

#include <linux/cper.h>
@@ -174,24 +175,33 @@ TRACE_EVENT(mc_event, 
 */



#define aer_correctable_errors					\

	{BIT(0),	"Receiver Error"},		\

	{BIT(6),	"Bad TLP"},			\

	{BIT(7),	"Bad DLLP"},			\

	{BIT(8),	"RELAY_NUM Rollover"},		\

	{BIT(12),	"Replay Timer Timeout"},	\

	{BIT(13),	"Advisory Non-Fatal"}

	{PCI_ERR_COR_RCVR,	"Receiver Error"},		\

	{PCI_ERR_COR_BAD_TLP,	"Bad TLP"},			\

	{PCI_ERR_COR_BAD_DLLP,	"Bad DLLP"},			\

	{PCI_ERR_COR_REP_ROLL,	"RELAY_NUM Rollover"},		\

	{PCI_ERR_COR_REP_TIMER,	"Replay Timer Timeout"},	\

	{PCI_ERR_COR_ADV_NFAT,	"Advisory Non-Fatal Error"},	\

	{PCI_ERR_COR_INTERNAL,	"Corrected Internal Error"},	\

	{PCI_ERR_COR_LOG_OVER,	"Header Log Overflow"}



#define aer_uncorrectable_errors				\

	{BIT(4),	"Data Link Protocol"},		\

	{BIT(12),	"Poisoned TLP"},		\

	{BIT(13),	"Flow Control Protocol"},	\

	{BIT(14),	"Completion Timeout"},		\

	{BIT(15),	"Completer Abort"},		\

	{BIT(16),	"Unexpected Completion"},	\

	{BIT(17),	"Receiver Overflow"},		\

	{BIT(18),	"Malformed TLP"},		\

	{BIT(19),	"ECRC"},			\

	{BIT(20),	"Unsupported Request"}

	{PCI_ERR_UNC_UND,	"Undefined"},			\

	{PCI_ERR_UNC_DLP,	"Data Link Protocol Error"},	\

	{PCI_ERR_UNC_SURPDN,	"Surprise Down Error"},		\

	{PCI_ERR_UNC_POISON_TLP,"Poisoned TLP"},		\

	{PCI_ERR_UNC_FCP,	"Flow Control Protocol Error"},	\

	{PCI_ERR_UNC_COMP_TIME,	"Completion Timeout"},		\

	{PCI_ERR_UNC_COMP_ABORT,"Completer Abort"},		\

	{PCI_ERR_UNC_UNX_COMP,	"Unexpected Completion"},	\

	{PCI_ERR_UNC_RX_OVER,	"Receiver Overflow"},		\

	{PCI_ERR_UNC_MALF_TLP,	"Malformed TLP"},		\

	{PCI_ERR_UNC_ECRC,	"ECRC Error"},			\

	{PCI_ERR_UNC_UNSUP,	"Unsupported Request Error"},	\

	{PCI_ERR_UNC_ACSV,	"ACS Violation"},		\

	{PCI_ERR_UNC_INTN,	"Uncorrectable Internal Error"},\

	{PCI_ERR_UNC_MCBTLP,	"MC Blocked TLP"},		\

	{PCI_ERR_UNC_ATOMEG,	"AtomicOp Egress Blocked"},	\

	{PCI_ERR_UNC_TLPPRE,	"TLP Prefix Blocked Error"}



TRACE_EVENT(aer_event,

	TP_PROTO(const char *dev_name,

include/uapi/linux/pci_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -631,7 +631,7 @@ 


/* Advanced Error Reporting */

#define PCI_ERR_UNCOR_STATUS	4	/* Uncorrectable Error Status */

#define  PCI_ERR_UNC_TRAIN	0x00000001	/* Training */

#define  PCI_ERR_UNC_UND	0x00000001	/* Undefined */

#define  PCI_ERR_UNC_DLP	0x00000010	/* Data Link Protocol */

#define  PCI_ERR_UNC_SURPDN	0x00000020	/* Surprise Down */

#define  PCI_ERR_UNC_POISON_TLP	0x00001000	/* Poisoned TLP */