Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1104528b authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/host-designware' into next

* pci/host-designware:
  PCI: designware: Add get_msi_data() to pcie_host_ops
  PCI: designware: Rename get_msi_data() to get_msi_addr()
  PCI: designware: Fix IO resource end address calculation
  PCI: designware: Fix configuration base address when using 'reg'
  PCI: designware: Use NULL instead of false

[bhelgaas: Fixup keystone for "PCI: designware: Rename get_msi_data() to
get_msi_addr()"]
parents c0ed74e9 24832b4d
Loading
Loading
Loading
Loading
+1 −1
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
	*bit_pos = offset >> 3;
}

u32 ks_dw_pcie_get_msi_data(struct pcie_port *pp)
u32 ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
{
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);

+1 −1
Original line number Diff line number Diff line
@@ -287,7 +287,7 @@ static struct pcie_host_ops keystone_pcie_host_ops = {
	.host_init = ks_pcie_host_init,
	.msi_set_irq = ks_dw_pcie_msi_set_irq,
	.msi_clear_irq = ks_dw_pcie_msi_clear_irq,
	.get_msi_data = ks_dw_pcie_get_msi_data,
	.get_msi_addr = ks_dw_pcie_get_msi_addr,
	.msi_host_init = ks_dw_pcie_msi_host_init,
	.scan_bus = ks_dw_pcie_v3_65_scan_bus,
};
+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ struct keystone_pcie {

/* Keystone DW specific MSI controller APIs/definitions */
void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset);
u32 ks_dw_pcie_get_msi_data(struct pcie_port *pp);
u32 ks_dw_pcie_get_msi_addr(struct pcie_port *pp);

/* Keystone specific PCI controller APIs */
void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);
+10 −7
Original line number Diff line number Diff line
@@ -361,12 +361,17 @@ static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
	 */
	desc->msi_attrib.multiple = msgvec;

	if (pp->ops->get_msi_data)
		msg.address_lo = pp->ops->get_msi_data(pp);
	if (pp->ops->get_msi_addr)
		msg.address_lo = pp->ops->get_msi_addr(pp);
	else
		msg.address_lo = virt_to_phys((void *)pp->msi_data);
	msg.address_hi = 0x0;

	if (pp->ops->get_msi_data)
		msg.data = pp->ops->get_msi_data(pp, pos);
	else
		msg.data = pos;

	write_msi_msg(irq, &msg);

	return 0;
@@ -430,7 +435,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)

		/* Find the untranslated configuration space address */
		index = of_property_match_string(np, "reg-names", "config");
		addrp = of_get_address(np, index, false, false);
		addrp = of_get_address(np, index, NULL, NULL);
		pp->cfg0_mod_base = of_read_number(addrp, ns);
		pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
	} else {
@@ -454,7 +459,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
			pp->io.end = min_t(resource_size_t,
					   IO_SPACE_LIMIT,
					   range.pci_addr + range.size
					   + global_io_offset);
					   + global_io_offset - 1);
			pp->io_size = resource_size(&pp->io);
			pp->io_bus_addr = range.pci_addr;
			pp->io_base = range.cpu_addr;
@@ -510,7 +515,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
	pp->mem_base = pp->mem.start;

	if (!pp->va_cfg0_base) {
		pp->cfg0_base = pp->cfg.start;
		pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
						pp->cfg0_size);
		if (!pp->va_cfg0_base) {
@@ -520,7 +524,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
	}

	if (!pp->va_cfg1_base) {
		pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
		pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
						pp->cfg1_size);
		if (!pp->va_cfg1_base) {
+2 −1
Original line number Diff line number Diff line
@@ -70,7 +70,8 @@ struct pcie_host_ops {
	void (*host_init)(struct pcie_port *pp);
	void (*msi_set_irq)(struct pcie_port *pp, int irq);
	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
	u32 (*get_msi_data)(struct pcie_port *pp);
	u32 (*get_msi_addr)(struct pcie_port *pp);
	u32 (*get_msi_data)(struct pcie_port *pp, int pos);
	void (*scan_bus)(struct pcie_port *pp);
	int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
};