Merge branches 'pci/host-altera', 'pci/host-designware', 'pci/host-generic',...

* Altera PCIe MSI controller

Required properties:

- compatible:	should contain "altr,msi-1.0"

- reg:		specifies the physical base address of the controller and

		the length of the memory mapped region.

- reg-names:	must include the following entries:

		"csr": CSR registers

		"vector_slave": vectors slave port region

- interrupt-parent:	interrupt source phandle.

- interrupts:	specifies the interrupt source of the parent interrupt

		controller. The format of the interrupt specifier depends on the

		parent interrupt controller.

- num-vectors:	number of vectors, range 1 to 32.

- msi-controller:	indicates that this is MSI controller node

Example

msi0: msi@0xFF200000 {

	compatible = "altr,msi-1.0";

	reg = <0xFF200000 0x00000010

		0xFF200010 0x00000080>;

	reg-names = "csr", "vector_slave";

	interrupt-parent = <&hps_0_arm_gic_0>;

	interrupts = <0 42 4>;

	msi-controller;

	num-vectors = <32>;

};

* Altera PCIe controller

Required properties:

- compatible :	should contain "altr,pcie-root-port-1.0"

- reg:		a list of physical base address and length for TXS and CRA.

- reg-names:	must include the following entries:

		"Txs": TX slave port region

		"Cra": Control register access region

- interrupt-parent:	interrupt source phandle.

- interrupts:	specifies the interrupt source of the parent interrupt controller.

		The format of the interrupt specifier depends on the parent interrupt

		controller.

- device_type:	must be "pci"

- #address-cells:	set to <3>

- #size-cells:	set to <2>

- #interrupt-cells:	set to <1>

- ranges:		describes the translation of addresses for root ports and standard

		PCI regions.

- interrupt-map-mask and interrupt-map: standard PCI properties to define the

		mapping of the PCIe interface to interrupt numbers.

Optional properties:

- msi-parent:	Link to the hardware entity that serves as the MSI controller for this PCIe

		controller.

- bus-range:	PCI bus numbers covered

Example

	pcie_0: pcie@0xc00000000 {

		compatible = "altr,pcie-root-port-1.0";

		reg = <0xc0000000 0x20000000>,

			<0xff220000 0x00004000>;

		reg-names = "Txs", "Cra";

		interrupt-parent = <&hps_0_arm_gic_0>;

		interrupts = <0 40 4>;

		interrupt-controller;

		#interrupt-cells = <1>;

		bus-range = <0x0 0xFF>;

		device_type = "pci";

		msi-parent = <&msi_to_gic_gen_0>;

		#address-cells = <3>;

		#size-cells = <2>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie_0 1>,

			            <0 0 0 2 &pcie_0 2>,

			            <0 0 0 3 &pcie_0 3>,

			            <0 0 0 4 &pcie_0 4>;

		ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000

			    0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;

	};

- phys: phandle of the PCIe PHY device

- phy-names: must be "pcie-phy"

- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done

by the ASIC after power on reset. In this case, SW needs to configure it

If the brcm,pcie-ob property is present, the following properties become

effective:

Required:

- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal

address used by the iProc PCIe core (not the PCIe address)

- brcm,pcie-ob-window-size: The outbound address mapping window size (in MB)

Optional:

- brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to

increase the outbound window size

Example:

	pcie0: pcie@18012000 {

		compatible = "brcm,iproc-pcie";

		phys = <&phy 0 5>;

		phy-names = "pcie-phy";

		brcm,pcie-ob;

		brcm,pcie-ob-oarr-size;

		brcm,pcie-ob-axi-offset = <0x00000000>;

		brcm,pcie-ob-window-size = <256>;

	};

	pcie1: pcie@18013000 {

	to define the mapping of the PCIe interface to interrupt

	numbers.

- num-lanes: number of lanes to use

- clocks: Must contain an entry for each entry in clock-names.

	See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

	- "pcie"

	- "pcie_bus"

Optional properties:

- num-lanes: number of lanes to use (this property should be specified unless

  the link is brought already up in BIOS)

- reset-gpio: gpio pin number of power good signal

- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to

  specify this property, to keep backwards compatibility a range of 0x00-0xff

  is assumed if not present)

- clocks: Must contain an entry for each entry in clock-names.

	See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

	- "pcie"

	- "pcie_bus"

- #size-cells    : Must be 2.

- reg            : The Configuration Space base address and size, as accessed

                   from the parent bus.

                   from the parent bus.  The base address corresponds to

                   the first bus in the "bus-range" property.  If no

                   "bus-range" is specified, this will be bus 0 (the default).

Properties of the /chosen node: